SP6655 datasheet(9/16 Pages) SIPEX

9 / 16 page

Date: 7/12/04

SP6655 High Efficiency 400mA Synchronous Buck Regulator

point RESET is held low until VOUT is above

regulation. Once RESET occurs TON minimum

is reset, and the TOFF one-shot is triggered to

blank the loop comparator from starting a new

charge cycle for a minimum period. This blank-

ing period occurs during the noisy LX transition

to discharge, where spurious comparator states

may occur. For TOFF > TBLANK the loop is in a

discharge or wait state until the loop comparator

starts the next charge cycle by DRVON going

high.

If an over current occurs during charge the loop

is interrupted and DRVON is RESET. The off-

time one-shot pulse width is widened to TOFF =

KOFF / VOUT, which holds the loop in discharge

for that time. At the end of the off-time the loop

is released and controlled by VOLOW. In this

manner maximum inductor current is controlled

on a cycle-by-cycle basis. An assertion of UVLO

(undervoltage lockout) or TSD (thermal shut-

down) holds the loop in no-charge until the fault

has ended.

On-Time Control - Discharge Phase

The discharge phase follows with the high side

PMOS switch opening and the low side NMOS

switch closing to provide a discharge path for

the inductor current. The decreasing inductor

current and the load current cause the output

voltage to drop. Under normal load conditions

when the inductor current is below the pro-

grammed limit, the off-time will continue until

the output voltage falls below the regulation

threshold, which initiates a new charge cycle via

the loop comparator.

The inductor current “floats” in continuous con-

duction mode. During this mode the inductor

peak current is below the programmed limit and

the valley current is above zero. This is to satisfy

load currents that are greater than half the mini-

mum current ripple. The current ripple, ILR, is

defined by the equation:

ILR ≈

KON

VIN - VOUT - IOUT * RCH

VIN - VOUT

where:

L = Inductor value

IOUT = Load current

RCH = PMOS on resistance, 0.3Ω typ.

If the IOUT * RCH term is negligible compared

with (VIN - VOUT), the above equation simplifies

to:

ILR ≈

KON

For most applications, the inductor current ripple

controlled by the SP6655 is constant regardless

of input and output voltage. Because the output

voltage ripple is equal to:

VOUT (ripple) = ILR * RESR

where:

RESR = ESR of the output capacitor

the output ripple of the SP6655 regulator is

independent of the input and output voltages.

For battery powered applications, where the

battery voltage changes significantly, the SP6655

provides constant output voltage ripple through-

out the battery lifetime. This greatly simplifies

the LC filter design.

The maximum loop frequency in CCM is de-

fined by the equation:

FLP ≈

(VIN - VOUT) * (VOUT + IOUT * RDC)

KON * [VIN + IOUT * (RDC - RCH)]

where:

FLP = CCM loop frequency

RDC = NMOS on resistance, 0.3Ω typ.

Ignoring conduction losses simplifies the loop

frequency to:

FLP ≈

VOUT

* (VIN - VOUT)

KON

VIN

AND’ing the loop comparator and the on-timer

reduces the switching frequency for load cur-

rents below half the inductor ripple current. This

increases light load efficiency. The minimum

on-time insures that the inductor current ripple

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