AD6673 datasheet(20/45 Pages) AD

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AD6673

Data Sheet

Rev. C | Page 20 of 45

An alternative to using a transformer-coupled input at frequencies

in the second Nyquist zone is to use an amplifier with variable

gain. The AD8375 or AD8376 digital variable gain amplifier

(DVGA) provides good performance for driving the AD6673.

Figure 31 shows an example of the AD8376 driving the AD6673

through a band-pass antialiasing filter.

AD8376

ADC

1µH

1nF

VPOS

VCM

15pF

68nH

20kΩ║2.5pF

301Ω

165Ω

5.1pF

3.9pF

180nH

1000pF

NOTES

1. ALL INDUCTORS ARE COILCRAFT® 0603CS COMPONENTS WITH THE

EXCEPTION OF THE 1µH CHOKE INDUCTORS (COILCRAFT 0603LS).

2. FILTER VALUES SHOWN ARE FOR A 20MHz BANDWIDTH FILTER

CENTERED AT 140MHz.

180nH

220nH

Figure 31. Differential Input Configuration Using the AD8376

VOLTAGE REFERENCE

A stable and accurate voltage reference is built into the AD6673.

The full-scale input range can be adjusted by varying the reference

voltage via the SPI. The input span of the ADC tracks the

reference voltage changes linearly.

CLOCK INPUT CONSIDERATIONS

The AD6673 has two options for deriving the input sampling

clock, a differential Nyquist sampling clock input or an RF clock

input (which is internally divided by 4). The clock input is selected

in Register 0x09 and, by default, is configured for the Nyquist clock

input. For optimum performance, clock the AD6673 Nyquist

sample clock input, CLK+ and CLK−, with a differential signal.

The signal is typically ac-coupled into the CLK+ and CLK− pins

via a transformer or via capacitors. These pins are biased internally

(see Figure 32) and require no external bias. If the clock inputs

are floated, CLK− is pulled slightly lower than CLK+ to prevent

spurious clocking.

Nyquist Clock Input Options

The AD6673 Nyquist clock input supports a differential clock

between 40 MHz to 625 MHz. The clock input structure supports

differential input voltages from 0.3 V to 3.6 V and is therefore

compatible with various logic family inputs, such as CMOS,

LVDS, and LVPECL. A sine wave input is also accepted, but

higher slew rates typically provide optimal performance. Clock

source jitter is a critical parameter that can affect performance, as

described in the Jitter Considerations section. If the inputs are

floated, pull the CLK− pin low to prevent spurious clocking.

The Nyquist clock input pins, CLK+ and CLK−, are internally

biased to 0.9 V and have a typical input impedance of 4 pF in

parallel with 10 kΩ (see Figure 32). The input clock is typically

ac-coupled to CLK+ and CLK−. Some typical clock drive circuits

are presented in Figure 33 through Figure 36 for reference.

AVDD

CLK+

4pF

CLK–

0.9V

Figure 32. Equivalent Nyquist Clock Input Circuit

For applications where a single-ended low jitter clock between

40 MHz to 200 MHz is available, an RF transformer is recom-

mended. An example using an RF transformer in the clock

network is shown in Figure 33. At frequencies above 200 MHz,

an RF balun is recommended, as seen in Figure 34. The back-to-

back Schottky diodes across the transformer secondary limit

clock excursions into the AD6673 to approximately 0.8 V p-p

differential. This limit helps prevent the large voltage swings of

the clock from feeding through to other portions of the AD6673,

yet preserves the fast rise and fall times of the clock, which are

critical to low jitter performance.

390pF

SCHOTTKY

DIODES:

HSMS2822

CLOCK

INPUT

50Ω

100Ω

CLK–

CLK+

ADC

Mini-Circuits®

ADT1-1WT, 1:1Z

XFMR

Figure 33. Transformer-Coupled Differential Clock (Up to 200 MHz)

390pF

CLOCK

INPUT

1nF

25Ω

CLK–

CLK+

SCHOTTKY

DIODES:

HSMS2822

ADC

Figure 34. Balun-Coupled Differential Clock (Up to 625 MHz)

In some cases, it is desirable to buffer or generate multiple

clocks from a single source. In those cases, Analog Devices, Inc.,

offers clock drivers with excellent jitter performance. Figure 35

shows a typical PECL driver circuit that uses PECL drivers such

as the AD9510, AD9511, AD9512, AD9513, AD9514, AD9515,

AD9516-0, AD9516-1, AD9516-2, AD9516-3, AD9516-4,

AD9516-5, AD9517-0, AD9517-1, AD9517-2, AD9517-3,

AD9517-4, AD9518-0, AD9518-1, AD9518-2, AD9518-3,

AD9518-4, AD9520-0, AD9520-1, AD9520-2, AD9520-3,

AD9520-4, AD9520-5, AD9522-0, AD9522-1, AD9522-2,

AD9522-3, AD9522-4, AD9522-5, AD9523, AD9524, ADCLK905,

ADCLK907, and ADCLK925.

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