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ADP195ACPZ-R7 Folha de dados(PDF) 9 Page - Analog Devices |
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ADP195ACPZ-R7 Folha de dados(HTML) 9 Page - Analog Devices |
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9 / 12 page ![]() Data Sheet ADP195 Rev. C | Page 9 of 12 THEORY OF OPERATION GND EN VIN VOUT ADP195 LEVEL SHIFT AND SLEW RATE CONTROL REVERSE POLARITY PROTECTION Figure 21. Functional Block Diagram The ADP195 is a high-side PMOS load switch. It is designed for supply operation between 1.1 V to 3.6 V. The PMOS load switch is designed for low on resistance, 65 mΩ at VIN = 1.8 V and supports greater than 1 A of continuous current. It is a low quiescent current device with a nominal 4 MΩ pull-down resistor on its enable pin (EN). The reverse current protection circuitry prevents current flow backward through the ADP195 when the output voltage is greater than the input voltage. A comparator senses the difference between the input and output voltages. When the difference between the input voltage and output voltage exceeds 75 mV, the body of the pFET is switched to VOUT and is turned off or opened; that is, the gate is connected to VOUT. The packaging is a space-saving 1.0 mm × 1.0 mm, 4-ball WLCSP. The ADP195 is also available in a 2 mm × 2 mm × 0.55 mm, 0.65 mm pitch LFCSP. |
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