ACT8941A datasheet(28/42 Pages) ACTIVE-SEMI

28 / 42 page

ACT8941A

Rev 0, 12-Mar-13

- 28 -

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PWRHLD) before nPBIN is de-asserted. If the

microprocessor is unable to complete its power-up

routine successfully before the user releases the

push-button, the ACT8941A automatically shuts the

system down. This provides protection against

accidental or momentary assertions of the push-

button. If desired, longer “push-and-hold” times can

be implemented by simply adding an additional time

delay before asserting PWRHLD.

Control Sequences

The ACT8941A features a variety of control

sequences that are optimized for supporting system

enable and disable sequences of

Rockchip

RK2906/RK2918 application processor.

Enabling/Disabling Sequence

A typical enable sequence is initiated whenever the

following conditions occurs:

1) nPBIN is asserted low via 50KΩ resistance, or

2) A valid input voltage is present at CHGIN2

The enable sequence begins by enabling REG1.

When the first regulator (REG1) reaches its power-

OK threshold, nRSTO is asserted low, resetting the

microprocessor. When REG1 reaches its power-OK

threshold for 2ms , REG4 and REG5 are enabled.

When REG1 reaches its power-OK threshold for

4ms , REG2 and REG3 are enabled. If REG1 is

above its power-OK threshold when the reset timer

expires, nRSTO is de-asserted, allowing the

microprocessor to begin its boot sequence. REG6

and REG7 can be enabled or disabled by I2C after

system powers up.

During the boot sequence, the microprocessor must

assert PWRHLD, holding the regulators to ensure

that the system remains powered after nPBIN is

released.

As with the enable sequence, a typical disable

sequence is initiated when the user presses the

push-button, which interrupts the processor via the

nPBSTAT output. The actual disable sequence is

completely

software-controlled,

but

typically

involved initiating various “clean-up” processes

before finally set MSTROFF[ ] bit to 1 to shut the

system down.

: Typical value shown, actual delay time may vary from (T-1ms) x 88% to T x 112%, where T is the typical delay time setting.

: Applicable only for ACT8941AQJ4##.

Figure 3:

Enable/Disable Sequence

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