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LAN9500AI Folha de dados(PDF) 17 Page - Microchip Technology

Nome de Peças LAN9500AI
Descrição Electrónicos  LAN950x USB 2.0 to 10/100 Ethernet Controller
PDF  213 Pages
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Fabricante Electrônico  MICROCHIP [Microchip Technology]
Página de início  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

LAN9500AI Folha de dados(HTML) 17 Page - Microchip Technology

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 2010 - 2015 Microchip Technology Inc.
DS00001875A-page 17
LAN950x
TABLE 3-3:
JTAG PINS
Num Pins
Name
Symbol
Buffer
Type
Description
1
JTAG Test Port
Reset
(Internal PHY
Mode)
nTRST
IS
(PU)
In internal PHY mode, this active-low pin functions
as the JTAG test port reset input.
Receive Data 0
(External PHY
Mode)
RXD0
IS
(PD)
In external PHY mode, this pin functions as the
receive data 0 input from the external PHY.
1
JTAG Test
Data Out
(Internal PHY
Mode)
TDO
O8
In internal PHY mode, this pin functions as the
JTAG data output.
PHY Reset
(External PHY
Mode)
nPHY_RST
O8
In external PHY mode, this active-low pin functions
as the PHY reset output.
1
JTAG Test
Clock
(Internal PHY
Mode)
TCK
IS
(PU)
In internal PHY mode, this pin functions as the
JTAG test clock. The maximum operating
frequency of this clock is 25MHz.
Receive Data 1
(External PHY
Mode)
RXD1
IS
(PD)
In external PHY mode, this pin functions as the
receive data 1 input from the external PHY.
1
JTAG Test
Mode Select
(Internal PHY
Mode)
TMS
IS
(PU)
In internal PHY mode, this pin functions as the
JTAG test mode select.
Receive Data 2
(External PHY
Mode)
RXD2
IS
(PD)
In external PHY mode, this pin functions as the
receive data 2 input from the external PHY.
1
JTAG Test
Data Input
(Internal PHY
Mode)
TDI
IS
(PU)
In internal PHY mode, this pin functions as the
JTAG data input.
Receive Data 3
(External PHY
Mode)
RXD3
IS
(PD)
In external PHY mode, this pin functions as the
receive data 3 input from the external PHY.



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