TAS2553_15 datasheet(25/58 Pages) TI

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LD(n)

LD (n+1)

BIT

CLOCK

DATA

RD(n)

WORD

CLOCK

LEFT CHANNEL

RIGHT CHANNEL

LD(n)

LD(n+1)

BIT

CLOCK

DATA

N N N

RD(n)

WORD

CLOCK

LEFT CHANNEL

RIGHT CHANNEL

LD(n)=n'thsampleofleftchanneldata

RD(n)=n'thsampleofrightchanneldata

LD(n)

LD (n+1)

BIT

CLOCK

DATA

N N N

RD(n)

WORD

CLOCK

LEFT CHANNEL

RIGHT CHANNEL

LD(n)=n'thsampleofleftchanneldata

RD(n)=n'thsampleofrightchanneldata

TAS2553

www.ti.com

SLAS978B – SEPTEMBER 2013 – REVISED FEBRUARY 2014

7.4.1.5 DSP Mode

Set Register 0x03, D(7:6) = 01 and Register 0x05, D(3:2) = 01 to place the TAS2553 audio interface into DSP

mode. In DSP mode, the rising edge of the word clock starts the data transfer with the left channel data first and

immediately followed by the right channel data. Each data bit is valid on the falling edge of the bit clock.

Figure 39. Timing Diagram for DSP Mode

Figure 40. Timing Diagram for DSP Mode with Offset=1

Figure 41. Timing Diagram for DSP Mode with Offset=0 and Inverted Bit Clock

For DSP mode, the number of bit-clocks per frame should be greater than twice the programmed word-length of

the data. Also the programmed offset value should be less than the number of bit-clocks per frame by at least

the programmed word-length of the data.

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