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AM4376 Folha de dados(PDF) 62 Page - Texas Instruments

Nome de Peças AM4376
Descrição Electrónicos  AM437x Sitara??Processors
PDF  261 Pages
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Fabricante Electrônico  TI [Texas Instruments]
Página de início  http://www.ti.com
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AM4376 Folha de dados(HTML) 62 Page - Texas Instruments

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AM4376, AM4377, AM4378, AM4379
SPRS851B – JUNE 2014 – REVISED APRIL 2015
www.ti.com
Table 4-10. Pin Attributes (ZDN Package) (continued)
BALL
BALL
BALL RESET
BUFFER
PULL
BALL
RESET
PIN NAME [2]
SIGNAL NAME [3]
MODE [4]
TYPE [5]
RESET
REL. MODE
POWER [9]
HYS [10]
STRENGTH
UP/DOWN
IO CELL [13]
NUMBER [1]
REL.
STATE [6]
[8]
(mA) [11]
TYPE [12]
STATE [7]
D24
xdma_event_intr0
xdma_event_intr0
0x0
I
OFF
PD (7)
Mode7
VDDSHV5
Yes
6
PU/PD
LVCMOS
ext_hw_trigger
0x1
I
timer4
0x2
IO
clkout1
0x3
O
spi1_cs1
0x4
IO
pr1_pru0_gpi16
0x5
I
EMU2
0x6
IO
gpio0_19
0x7
IO
pr1_mdio_data
0x8
IO
gpio5_28
0x9
IO
C24
xdma_event_intr1
xdma_event_intr1
0x0
I
OFF
PD
Mode7
VDDSHV5
Yes
6
PU/PD
LVCMOS
spi0_cs2
0x1
IO
tclkin
0x2
I
clkout2
0x3
O
timer7
0x4
IO
pr1_pru0_gpi16
0x5
I
EMU3
0x6
IO
gpio0_20
0x7
IO
pr1_mdio_mdclk
0x8
O
gpio5_29
0x9
IO
C25
XTALIN
OSC0_IN
0x0 (2)
I
Z
Z
Mode0
VDDS_OSC
Yes
NA
PD
LVCMOS
B25
XTALOUT
OSC0_OUT
0x0
O
Z
Z
Mode0
VDDS_OSC
NA
NA (11)
NA
LVCMOS
(1) An internal 10 kohm pullup is turned on when the oscillator is disabled. The oscillator is disabled by default after power is applied.
(2) An internal 15 kohm pulldown is turned on when the oscillator is disabled. The oscillator is enabled by default after power is applied.
(3) DSS_DATA[15:0] terminals are respectively SYSBOOT[15:0] inputs, latched on the rising edge of PWRONRSTn.
(4) DSS_HSYNC terminal is SYSBOOT[17] input, latched on the rising edge of PWRONRSTn.
(5) DSS_VSYNC terminal is SYSBOOT[16] input, latched on the rising edge of PWRONRSTn.
(6) Do not connect any signal, test point, or board trace to reserved signals.
(7) If sysboot[17] is low on the rising edge of PWRONRSTn, this terminal has an internal pulldown turned on after reset is released. If sysboot[17] is high on the rising edge or PWRONRSTn,
this terminal will initially be driven low after reset is released then it begins to toggle at the same frequency of the OSC0_IN terminal.
(8) Refer to the External Warm Reset section of the Technical Reference Manual for more information related to the operation of this terminal.
(9) Reset Release Mode = 7 if sysboot[17] is low. Mode = 3 if sysboot[17] is high.
(10) The input voltage thresholds for this input are not a function of VDDSHV3. Refer to the DC Electrical Characteristics section for details related to electrical parameters associated with this
input terminal
(11) This output should only be used to source the recommended crystal circuit.
(12) This parameter only applies when this USB PHY terminal is operating in UART2 mode.
62
Terminal Configuration and Functions
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