1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR

2

Rev D 2/17/15

8745B-21 DATA SHEET

Table 1. Pin Descriptions

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

Table 2. Pin Characteristics

Number

Name

Type

Description

1

CLK

Input

Pulldown

Non-inverting differential clock input.

2

nCLK

Input

Pullup

Inverting differential clock input.

3

MR

Input

Pulldown

Active HIGH Master Reset. When logic HIGH, the internal dividers are reset

causing the true output Q to go low and the inverted output nQ to go high.

When logic LOW, the internal dividers and the outputs are enabled.

LVCMOS / LVTTL interface levels.

4

nFBIN

Input

Pullup

Inverting differential feedback input to phase detector for regenerating clocks with

“Zero Delay.”

5

FBIN

Input

Pulldown

Non-inverted differential feedback input to phase detector for regenerating clocks

with “Zero Delay.”

6, 15,

19, 20

SEL2, SEL3,

SEL0 SEL1

Input

Pulldown

Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.

7, 11

Power

Output supply pins.

8, 9

nQFB/QFB

Output

Differential feedback output pair. LVDS interface levels.

10, 14

GND

Power

Power supply ground.

12, 13

nQ/Q

Output

Differential output pair. LVDS interface levels.

16

Power

Analog supply pin.

17

PLL_SEL

Input

Pullup

PLL select. Selects between the PLL and reference clock as the input to the

dividers. When LOW, selects reference clock. LVCMOS/LVTTL interface levels.

18

Power

Core supply pin.

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

Input Capacitance

4pF

Input Pullup Resistor

51

k



Input Pulldown Resistor

51

k

