IR36021 datasheet(7/41 Pages) IRF

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IR36021

DIGITAL POL BUCK CONTROLLER with I2C AND PMBus

Interface

February 27, 2013 | Rev 3.5

PIN DESCRIPTION

PIN #

PIN NAME

PIN DESCRIPTION

PGood2

Voltage Regulator Ready Output (Loop #2). Open‐drain output that asserts high when the VR has

completed soft‐start to Loop #2 boot voltage.

VSEN1

Voltage Sense Input Loop#1. This pin is connected directly to the VR output voltage of Loop #1 at

the load and should be routed differentially with VRTN

VRTN1

Voltage Sense Return Input Loop#1. This pin is connected directly to Loop#1 ground at the load

and should be routed differentially with VSEN.

RRES

Current Reference Resistor. A 1% resistor is connected to this pin to set an internal precision

current reference

TSEN

NTC Temperature Sense Input. An NTC network is connected to this pin to measure temperature.

V18A

1.8V Decoupling. Two capacitors on this pin provide decoupling for the internal 1.8V supply

PGood1

Voltage Regulator Ready Output (Loop #1). Open‐drain output that asserts high when the VR has

completed soft‐start to Loop #1 boot voltage.

EN2

VR Enable Input. ENABLE is an active high system input to power‐on the regulator, provided Vin

and Vcc are present. ENABLE is not pulled up on the controller. When ENABLE is pulled low, the

controller de‐asserts PGOOD2 and shuts down the regulator.

VINSEN

VIN Voltage Sense Input. This is used to detect a valid 5V‐12V supply voltage and measure the

input voltage to the VR.

VRHOT‐ICRIT

VRHOT_ICRIT# Output. Active low alert pin that can be programmed to assert if temperature or

average load current exceeds user‐definable thresholds.

EN1

VR Enable Input. ENABLE is an active high system input to power‐on the regulator, provided Vin

and Vcc are present. ENABLE is not pulled up on the controller. When ENABLE is pulled low, the

controller de‐asserts PGOOD1 and shuts down the regulator.

ADDR_PROT

Bus Address & I2C Bus Protection A resistor to ground on this pin defines the I2C address which is

latched when VCC becomes valid. Subsequently, this pin becomes a logic input to enable or disable

communication on the I2C bus,

SM_ALERT

SMBus Alert line

SM_DIO

Serial Data Line I/O. I2C bus bi‐directional serial data line.

SM_CLK

Serial Clock Line Input. I2C bus clock input.

PWM1a

Loop 1 Phase 1 Pulse Width Modulation Output. PWM signal pin which is connected to the input

of an external MOSFET gate driver. The power‐up state is high‐impedance until ENABLE goes

active. Refer to the TBD section for unused/disabled phases.

PWM1b

Loop 1 Phase 2 Pulse Width Modulation Output. PWM signal pin which is connected to the input

of an external MOSFET gate driver. The power‐up state is high‐impedance until ENABLE goes

active. Refer to the TBD section for unused/disabled phases.

PWM2

Loop 2 Pulse Width Modulation Output. PWM signal pin which is connected to the input of an

external MOSFET gate driver. The power‐up state is high‐impedance until ENABLE goes active.

Refer to the TBD section for unused/disabled phases.

VRTN2

Voltage Sense Return Input Loop#2. This pin is connected directly to Loop#2 ground at the load

and should be routed differentially with VSEN.

VSEN2

Voltage Sense Input Loop#1. This pin is connected directly to the VR output voltage of Loop #2 at

the load and should be routed differentially with VRTN

VCC

Input supply voltage. 3.3V supply to power the device

RCSM2

Resistor Current Sense Minus Loop 2. This pin is connected to an external network to set the

loadline slope, bandwidth and temperature compensation for Loop #2.

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