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LCL8052ACPD Folha de dados(PDF) 10 Page - Intersil Corporation

Nome de Peças LCL8052ACPD
Descrição Electrónicos  14-Bit/16-Bit, Microprocessor- Compatible, 2-Chip, A/D Converter
PDF  21 Pages
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Fabricante Electrônico  INTERSIL [Intersil Corporation]
Página de início  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

LCL8052ACPD Folha de dados(HTML) 10 Page - Intersil Corporation

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TABLE 1. DIRECT MODE TIMING REQUIREMENTS (Note: Not tested in production)
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNIT
tBEA
XBEN (Min) Pulse Width.
-
300
-
ns
tDAB
Data Access Time from XBEN.
-
300
-
ns
tDHB
Data Hold Time from XBEN.
-
200
-
ns
tCEA
CE/LD Min. Pulse Width.
-
350
-
ns
tDAC
Data Access Time from CE/LD.
-
350
-
ns
tDHC
Data Hold Time from CE/LD.
-
280
-
ns
tCWH
CLOCK 1 High Time.
-
1000
-
ns
TABLE 2. HANDSHAKE TIMING REQUIREMENTS (Note: Not tested in production)
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNIT
tMW
Mode Pulse (Min).
-
20
-
ns
tSM
Mode Pin Set-Up Time.
-
-150
-
ns
tME
Mode Pin High to Low Z CE/LD High Delay.
-
200
-
ns
tMB
Mode Pin High to XBEN Low Z (High) Delay.
-
200
-
ns
tCEL
Clock 1 High to CE/LD Low Delay.
-
700
-
ns
tCEH
Clock 1 High to CE/LD High Delay.
-
600
-
ns
tCBL
Clock 1 High to XBEN Low Delay.
-
900
-
ns
tCBH
Clock 1 High to XBEN High Delay.
-
700
-
ns
tCDH
Clock 1 High to Data Enabled Delay.
-
1100
-
ns
tCDL
Clock 1 Low to Data Disabled Delay.
-
1100
-
ns
tSS
Send ENABLE Set-Up Time.
-
-350
-
ns
tCBZ
Clock 1 High to XBEN Disabled Delay.
-
2000
-
ns
tCEZ
Clock 1 High to CE/LD Disabled Delay.
-
2000
-
ns
tCWH
Clock 1 High Time.
1250
1000
-
ns
ICL8052/ICL7104, ICL8068/ICL7104



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