AD9430_15 datasheet(25/44 Pages) AD

25 / 44 page

AD9430

Rev. E | Page 25 of 44

APPLICATION NOTES

THEORY OF OPERATION

The AD9430 architecture is optimized for high speed and ease

of use. The analog inputs drive an integrated high bandwidth

track-and-hold circuit that samples the signal prior to

quantization by the 12-bit core. For ease of use, the part

includes an on-board reference and input logic that accepts

TTL, CMOS, or LVPECL levels. The digital output logic levels

are user selectable as standard 3 V CMOS or LVDS (ANSI-644

compatible) via Pin S2.

ENCODE INPUT

Any high speed ADC is extremely sensitive to the quality of the

sampling clock provided by the user. A track-and-hold circuit is

essentially a mixer, and any noise, distortion, or timing jitter on

the clock is combined with the desired signal at the A/D output.

For that reason, considerable care has been taken in the design

of the clock inputs of the AD9430, and the user is advised to

give careful thought to the clock source.

The AD9430 has an internal clock duty cycle stabilization

circuit that locks to the rising edge of CLK+ and optimizes

timing internally. This allows for a wide range of input duty

cycles at the input without degrading performance. Jitter in

the rising edge of the input is still of paramount concern and

is not reduced by the internal stabilization circuit. The duty

cycle control loop does not function for clock rates less than

30 MHz nominally. The loop has a time constant associated

with it that needs to be considered in applications where the

clock rate can change dynamically, requiring a wait time of

1.5 μs to 5 μs after a dynamic clock frequency increase before

valid data is available. This circuit is always on and cannot be

disabled by the user.

The clock inputs are internally biased to 1.5 V (nominal) and

support either differential or single-ended signals. For best

dynamic performance, a differential signal is recommended. An

MC100LVEL16 performs well in the circuit to drive the clock

inputs, as illustrated in Figure 50. (For trace lengths >2 inches, a

standard LVPECL termination is recommended rather than the

simple pull-down as shown.) Note that for this low voltage

PECL device, the ac coupling is optional.

PECL

GATE

510

0.1

μF

0.1

μF

CLK–

AD9430

CLK+

Figure 50. Driving Clock Inputs with LVEL16

In interleaved mode, output data on Port A is offset from output

data changes on Port B by one-half output clock cycle, as shown

in Figure 51.

INTERLEAVED MODE

PARALLEL MODE

Figure 51.

Table 9. Output Select Coding

S11

S21

S41

S51

(Data Format Select)

(LVDS/CMOS Mode Select)2

(I/P Select)

(Full-Scale Select)3

Mode

Twos complement

Offset binary

Dual-mode CMOS interleaved

Dual-mode CMOS parallel

LVDS mode

Full scale = 0.768 V

Full scale = 1.536 V

1 X = don’t care.

2 S4 used in CMOS mode only (S2 = 0). S1 to S5 all have 30 kΩ resistive pull-downs on chip.

3 S5 full-scale adjust (see the

section).

Analog Input

AD9430 Folha de dados(PDF) 25 Page - Analog Devices

AD9430 Folha de dados(HTML) 25 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

Folha de dados Download

Ligação URL