AD9430_15 datasheet(7/44 Pages) AD

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AD9430

Rev. E | Page 7 of 44

DIGITAL SPECIFICATIONS

AVDD = 3.3 V, DRVDD = 3.3 V, TMIN = –40°C, TMAX = +85°C, unless otherwise noted.

Table 3.

Test

AD9430-170

AD9430-210

Parameter

Temp

Level

Min

Typ

Max

Min

Typ

Max

Unit

ENCODE AND DS INPUTS

(CLK+, CLK–, DS+, DS–)1

Differential Input Voltage2

Full

0.2

Common-Mode Voltage3

Full

1.375

1.5

1.575

1.375

1.5

1.575

Input Resistance

Full

3.2

5.5

6.5

3.2

5.5

6.5

kΩ

Input Capacitance

25°C

LOGIC INPUTS (S1, S2, S4, S5)

Logic 1 Voltage

Full

2.0

Logic 0 Voltage

Full

0.8

Logic 1 Input Current

Full

190

μA

Logic 0 Input Current

Full

μA

Input Resistance

25°C

kΩ

Input Capacitance

25°C

LOGIC OUTPUTS (CMOS Mode)

Logic 1 Voltage4

Full

DRVDD

–0.05

Logic 0 Voltage4

Full

0.05

LOGIC OUTPUTS (LVDS Mode)4, 5

VOD Differential Output Voltage

Full

247

454

247

454

VOS Output Offset Voltage

Full

1.125

1.375

1.125

1.375

Output Coding

Twos complement or binary

1 ENCODE (Clock) and DS inputs identical on the chip. See the

section.

Equivalent Circuits

2 All ac specifications tested by driving CLK+ and CLK– differentially, |(CLK+) – (CLK–)| > 200 mV.

3 ENCODE (Clock) inputs’ common-mode can be externally set, such that 0.9 V < (CLK+ or CLK−) < 2.6 V.

4 Digital output logic levels: DRVDD = 3.3 V, CLOAD = 5 pF.

5 LVDS RTERM = 100 Ω, LVDS output current set resistor (RSET) = 3.74 kΩ (1% tolerance).

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