AD9760 datasheet(13/23 Pages) AD

13 / 23 page

AD9760

–13–

REV. B

The optimum distortion performance for any reconstructed

waveform is obtained with a 0.1

µF external capacitor installed.

Thus, if IREF is fixed for an application, a 0.1

µF ceramic chip

capacitor is recommended. Also, since the control amplifier is

optimized for low power operation, multiplying applications

requiring large signal swings should consider using an external

control amplifier to enhance the application’s overall large signal

multiplying bandwidth and/or distortion performance.

There are two methods in which IREF can be varied for a fixed

RSET. The first method is suitable for a single-supply system in

which the internal reference is disabled, and the common-mode

voltage of REFIO is varied over its compliance range of 1.25 V

to 0.10 V. REFIO can be driven by a single-supply amplifier or

DAC, allowing IREF to be varied for a fixed RSET. Since the

input impedance of REFIO is approximately 1 M

Ω, a simple,

low cost R-2R ladder DAC configured in the voltage mode

topology may be used to control the gain. This circuit is shown

in Figure 43 using the AD7524 and an external 1.2 V reference,

the AD1580.

The second method may be used in a dual-supply system in

which the common-mode voltage of REFIO is fixed and IREF is

varied by an external voltage, VGC, applied to RSET via an ampli-

fier. An example of this method is shown in Figure 44 where

the internal reference is used to set the common-mode voltage

of the control amplifier to 1.20 V. The external voltage, VGC, is

referenced to ACOM and should not exceed 1.2 V. The value

of RSET is such that IREFMAX and IREFMIN do not exceed 62.5

µA

and 625

µA, respectively. The associated equations in Figure 44

can be used to determine the value of RSET.

50pF

COMP1

+1.2V REF

AVDD

REFLO

CURRENT

SOURCE

ARRAY

AVDD

REFIO

FS ADJ

RSET

AD9760

IREF

OPTIONAL

BANDLIMITING

CAPACITOR

VGC

1 F

IREF = (1.2 – VGC)/RSET

WITH VGC < VREFIO AND 62.5 A

IREF

625A

Figure 44. Dual-Supply Gain Control Circuit

In some applications, the user may elect to use an external con-

trol amplifier to enhance the multiplying bandwidth, distortion

performance and/or settling time. External amplifiers capable of

driving a 50 pF load such as the AD817 are suitable for this

purpose. It is configured in such a way that it is in parallel with

the weaker internal reference amplifier as shown in Figure 45.

In this case, the external amplifier simply overdrives the weaker

reference control amplifier. Also, since the internal control

amplifier has a limited current output, it will sustain no damage

if overdriven.

50pF COMP1

+1.2V REF

AVDD

REFLO

CURRENT

SOURCE

ARRAY

AVDD

REFIO

FS ADJ

RSET

AD9760

VREF

INPUT

EXTERNAL

CONTROL AMPLIFIER

Figure 45. Configuring an External Reference Control

Amplifier

ANALOG OUTPUTS

The AD9760 produces two complementary current outputs,

IOUTA and IOUTB, which may be configured for single-ended or

differential operation. IOUTA and IOUTB can be converted into

complementary single-ended voltage outputs, VOUTA and VOUTB,

via a load resistor, RLOAD, as described in the DAC Transfer

Function section by Equations 5 through 8. The differential

voltage, VDIFF, existing between VOUTA and VOUTB can also be

converted to a single-ended voltage via a transformer or differ-

ential amplifier configuration. The ac performance of the AD9760

is optimum and specified using a differential transformer

coupled output in which the voltage swing at IOUTA and IOUTB is

limited to

±0.5 V. If a single-ended unipolar output is desirable,

IOUTA should be selected.

The distortion and noise performance of the AD9760 can be

enhanced when the AD9760 is configured for differential opera-

tion. The common-mode error sources of both IOUTA and IOUTB

can be significantly reduced by the common-mode rejection of a

transformer or differential amplifier. These common-mode

error sources include even-order distortion products and noise.

1.2V

50pF

COMP1

+1.2V REF

AVDD

REFLO

CURRENT

SOURCE

ARRAY

AVDD

REFIO

FS ADJ

RSET

AD9760

IREF =

VREF/RSET

AVDD

OPTIONAL

BANDLIMITING

CAPACITOR

VREF

VDD

RFB

OUT1

OUT2

AGND

DB7–DB0

AD7524

AD1580

0.1V TO 1.2V

Figure 43. Single-Supply Gain Control Circuit

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