AD9760 datasheet(12/23 Pages) AD

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AD9760

–12–

REV. B

The differential voltage, VDIFF, appearing across IOUTA and

IOUTB is:

VDIFF = (IOUTA – IOUTB)

× RLOAD

(7)

Substituting the values of IOUTA, IOUTB and IREF; VDIFF can be

expressed as:

VDIFF = {(2 DAC CODE – 1023)/1024}

(32 RLOAD/RSET)

× V

REFIO

(8)

These last two equations highlight some of the advantages of

operating the AD9760 differentially. First, the differential op-

eration will help cancel common-mode error sources associated

with IOUTA and IOUTB such as noise, distortion and dc offsets.

Second, the differential code dependent current and subsequent

voltage, VDIFF, is twice the value of the single-ended voltage

output (i.e., VOUTA or VOUTB), thus providing twice the signal

power to the load.

Note, the gain drift temperature performance for a single-ended

(VOUTA and VOUTB) or differential output (VDIFF) of the AD9760

can be enhanced by selecting temperature tracking resistors for

RLOAD and RSET due to their ratiometric relationship as shown

in Equation 8.

REFERENCE OPERATION

The AD9760 contains an internal 1.20 V bandgap reference

that can be easily disabled and overridden by an external refer-

ence. REFIO serves as either an input or output depending on

whether the internal or an external reference is selected. If

REFLO is tied to ACOM, as shown in Figure 40, the internal

reference is activated and REFIO provides a 1.20 V output. In

this case, the internal reference must be compensated externally

with a ceramic chip capacitor of 0.1

µF or greater from REFIO

to REFLO. Also, REFIO should be buffered with an external

amplifier having an input bias current less than 100 nA if any

additional loading is required.

50pF

COMP1

+1.2V REF

AVDD

REFLO

CURRENT

SOURCE

ARRAY

0.1 F

+5V

REFIO

FS ADJ

0.1 F

AD9760

ADDITIONAL

LOAD

OPTIONAL

EXTERNAL

REF BUFFER

Figure 40. Internal Reference Configuration

The internal reference can be disabled by connecting REFLO to

AVDD. In this case, an external reference may be applied to

REFIO as shown in Figure 41. The external reference may

provide either a fixed reference voltage to enhance accuracy and

drift performance or a varying reference voltage for gain control.

Note that the 0.1

µF compensation capacitor is not required

since the internal reference is disabled, and the high input im-

pedance (i.e., 1 M

Ω) of REFIO minimizes any loading of the

external reference.

REFERENCE CONTROL AMPLIFIER

The AD9760 also contains an internal control amplifier that is

used to regulate the DAC’s full-scale output current, IOUTFS.

The control amplifier is configured as a V-I converter as shown

in Figure 41, so that its current output, IREF, is determined by

the ratio of the VREFIO and an external resistor, RSET, as stated

in Equation 4. IREF is copied over to the segmented current

sources with the proper scaling factor to set IOUTFS as stated in

Equation 3.

50pF

COMP1

+1.2V REF

AVDD

REFLO

CURRENT

SOURCE

ARRAY

0.1 F

AVDD

REFIO

FS ADJ

RSET

AD9760

EXTERNAL

REF

IREF =

VREFIO/RSET

AVDD

REFERENCE

CONTROL

AMPLIFIER

VREFIO

Figure 41. External Reference Configuration

The control amplifier allows a wide (10:1) adjustment span of

IOUTFS over a 2 mA to 20 mA range by setting IREF between

62.5

µA and 625 µA. The wide adjustment span of I

OUTFS pro-

vides several application benefits. The first benefit relates

directly to the power dissipation of the AD9760, which is

proportional to IOUTFS (refer to the Power Dissipation section).

The second benefit relates to the 20 dB adjustment, which is

useful for system gain control purposes.

The small signal bandwidth of the reference control amplifier is

approximately 1.4 MHz and can be reduced by connecting an

external capacitor between COMP1 and AVDD. The output of

the control amplifier, COMP1, is internally compensated via a

50 pF capacitor that limits the control amplifier small-signal

bandwidth and reduces its output impedance. Any additional

external capacitance further limits the bandwidth and acts as a

filter to reduce the noise contribution from the reference ampli-

fier. Figure 42 shows the relationship between the external

capacitor and the small signal –3 dB bandwidth of the refer-

ence amplifier. Since the –3 dB bandwidth corresponds to the

dominant pole, and hence the time constant, the settling time of

the control amplifier to a stepped reference input response can

be approximated.

COMP1 CAPACITOR – nF

1000

0.1

1000

100

Figure 42. External COMP1 Capacitor vs. –3 dB Bandwidth

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