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CY7C0430V
PRELIMINARY
13
Bank Select Read[12, 13]
Read-to-Write-to-Read (OE = VIL)
[14, 15, 16, 17]
Notes:
12. In this depth expansion example, B1 represents Bank #1 and B2 is Bank #2; Each Bank consists of one Cypress Quadport device from this data sheet.
ADDRESS(B1) = ADDRESS(B2).
13. LB = UB = OE = CNTLD = VIL; MRST= CNTRST= MKLD = VIH.
14. Output state (HIGH, LOW, or High-Impedance) is determined by the previous cycle control signals.
15. LB = UB = CNTLD = VIL; MRST= CNTRST= MKLD =VIH.
16. Addresses do not have to be accessed sequentially since CNTLD= VIL constantly loads the address on the rising edge of the CLK; numbers are for reference only.
17. During “No operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity.
Switching Waveforms (continued)
Q3
Q1
Q0
Q2
A0
A1
A2
A3
A4
A5
Q4
A0
A1
A2
A3
A4
A5
tSA
tHA
tSC
tHC
tSA
tHA
tSC
tHC
tSC
tHC
tSC tHC
tCKHZ
tDC
tDC
tCD2
tCKLZ
tCD2
tCD2
tCKHZ
tCKLZ
tCD2
tCKHZ
tCKLZ
tCD2
tCH2
tCL2
tCYC2
CLK
ADDRESS(B1)
CE(B1)
DATAOUT(B2)
DATAOUT(B1)
ADDRESS(B2)
CE(B2)
tCYC2
tCL2
tCH2
tHC
tSC
tHW
tSW
tHA
tSA
tHW
tSW
tCD2
tCKHZ
tSD tHD
tCKLZ
tCD2
NO OPERATION
WRITE
READ
READ
CLK
CE
R/W
ADDRESS
DATAIN
DATAOUT
An
An+1
An+2
An+2
Dn+2
An+3
An+4
Qn
Qn+3
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