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CY7C0430V
PRELIMINARY
9
Switching Characteristics Over the Industrial Operating Range
Parameter
Description
CY7C0430V
Unit
–133
–100
Min.
Max.
Min.
Max.
fMAX2
Maximum Frequency
133
100
MHz
tCYC2
Clock Cycle Time
7.5
10
ns
tCH2
Clock HIGH Time
3
4
ns
tCL2
Clock LOW Time
3
4
ns
tR
Clock Rise Time
2
3
ns
tF
Clock Fall Time
2
3
ns
tSA
Address Set-up Time
2.5
3
ns
tHA
Address Hold Time
0.5
0.5
ns
tSC
Chip Enable Set-up Time
2.5
3
ns
tHC
Chip Enable Hold Time
0.5
0.5
ns
tSW
R/W Set-up Time
2.5
3
ns
tHW
R/W Hold Time
0.5
0.5
ns
tSD
Input Data Set-up Time
2.5
3
ns
tHD
Input Data Hold Time
0.5
0.5
ns
tSB
Byte Set-up Time
2.5
3
ns
tHB
Byte Hold Time
0.5
0.5
ns
tSCLD
CNTLD Set-up Time
2.5
3
ns
tHCLD
CNTLD Hold Time
0.5
0.5
ns
tSCINC
CNTINC Set-up Time
2.5
3
ns
tHCINC
CNTINC Hold Time
0.5
0.5
ns
tSCRST
CNTRST Set-up Time
2.5
3
ns
tHCRST
CNTRST Hold Time
0.5
0.5
ns
tSCRD
CNTRD Set-up Time
2.5
3
ns
tHCRD
CNTRD Hold Time
0.5
0.5
ns
tSMLD
MKLD Set-up Time
2.5
3
ns
tHMLD
MKLD Hold Time
0.5
0.5
ns
tSMRD
MKRD Set-up Time
2.5
3
ns
tHMRD
MKRD Hold Time
0.5
0.5
ns
tOE
Output Enable to Data Valid
6.5
8
ns
tOLZ
[5]
OE to LOW Z
1
1
ns
tOHZ
[5]
OE to HIGH Z
1
6
1
7
ns
tCD2
Clock to Data Valid
4.7
5
ns
tCA2
Clock to Counter Address Readback Valid
4.7
5
ns
tCM2
Clock to Mask Register readback Valid
4.7
5
ns
tDC
Data Output Hold After Clock HIGH
1
1
ns
tCKHZ
[6]
Clock HIGH to Output High Z
1
4.8
1
6.8
ns
tCKLZ
[6]
Clock HIGH to Output LOW Z
1
1
ns
tSINT
Clock to INT Set Time
1
6.5
1
8
ns
tRINT
Clock to INT Reset Time
1
6.5
1
8
ns
tSCINT
Clock to CNTINT Set Time
1
6.5
1
8
ns
tRCINT
Clock to CNTINT Reset Time
1
6.5
1
8
ns
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