RL78 datasheet(61/61 Pages) RENESAS

61 / 61 page

RL78/G14

2. ELECTRICAL SPECIFICATIONS

R01DS0053EJ0100 Rev. 1.00

Page 61 of 97

Feb 21, 2012

Caution

The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.

2.4

AC Characteristics

2.4.1

Basic operation

Note

The following conditions are required for low voltage interface when EVDD0 < VDD

1.8 V

 EVDD0 < 2.7 V : MIN. 125 ns

1.6 V

 EVDD0 < 1.8 V : MIN. 250 ns

Remark

fMCK: Timer array unit operation clock frequency

(Operation clock to be set by the CKSmn bit of timer mode register mn (TMRmn). m: Unit number (m = 0, 1), n: Channel

number (n = 0 to 3))

(TA = -40 to +85

C, 1.6 V  EVDD0 = EVDD1  VDD

 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)

(1/2)

Items

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Instruction cycle

(minimum instruction

execution time)

TCY

Main system

clock (fMAIN)

operation

High-speed

main mode

2.7 V

 VDD  5.5 V

0.03125

s

2.4 V

 VDD < 2.7 V

0.0625

s

Low voltage

main mode

1.6 V

 VDD  5.5 V

0.25

s

Low-speed

main mode

1.8 V

 VDD  5.5 V

0.125

s

Subsystem clock (fSUB) operation

1.8 V

 VDD  5.5 V

28.5

30.5

31.3

s

In the self

programming

mode

High-speed

main mode

2.7 V

 VDD  5.5 V

0.03125

s

2.4 V

 VDD < 2.7 V

0.0625

s

Low voltage

main mode

1.8 V

 VDD  5.5 V

0.25

s

Low-speed

main mode

1.8 V

 VDD  5.5 V

0.125

s

External main system

clock frequency

fEX

2.7 V

 VDD  5.5 V

1.0

20.0

MHz

1.8 V

 VDD < 2.7 V

1.0

8.0

MHz

1.6 V

 VDD < 1.8 V

1.0

4.0

MHz

fEXS

kHz

External main system

clock input high-level

width, low-level width

tEXH,

tEXL

2.7 V

 VDD  5.5 V

1.8 V

 VDD < 2.7 V

1.6 V

 VDD < 1.8 V

120

tEXHS,

tEXLS

13.7

s

TI00 to TI03, TI10 to

TI13 input high-level

width, low-level width

tTIH, tTIL

1/fMCK + 10

Note

Timer RJ input cycle

TRJIO

2.7 V

 EVDD0  5.5 V

100

1.8 V

 EVDD0 < 2.7 V

300

1.6 V

 EVDD0 < 1.8 V

500

Timer RJ input high-

level width, low-level

width

fWH, fWL

TRJIO

2.7 V

 EVDD0  5.5 V

1.8 V

 EVDD0 < 2.7 V

120

1.6 V

 EVDD0 < 1.8 V

200

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