RL78 datasheet(34/61 Pages) RENESAS

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RL78/G14

1. OUTLINE

R01DS0053EJ0100 Rev. 1.00

Page 34 of 97

Feb 21, 2012

(2/2)

Note

The illegal instruction is generated when instruction code FFH is executed.

Reset by the illegal instruction execution not is issued by emulation with the in-circuit emulator or on-chip debug

emulator.

Item

30-pin

32-pin

36-pin

40-pin

R5F104Ax

(x = F, G)

R5F104Bx

(x = F, G)

R5F104Cx

(x = F, G)

R5F104Ex

(x = F to H)

Clock output/buzzer output

222

[30-pin, 32-pin, 36-pin products]

• 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz

(Main system clock: fMAIN = 20 MHz operation)

[40-pin products]

• 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz

(Main system clock: fMAIN = 20 MHz operation)

• 256 Hz, 512 Hz, 1.024 kHz, 2.048 kHz, 4.096 kHz, 8.192 kHz, 16.384 kHz, 32.768 kHz

(Subsystem clock: fSUB = 32.768 kHz operation)

8/10-bit resolution A/D converter

8 channels

9 channels

D/A converter

1 channel

2 channels

Comparator

2 channels

Serial interface

[30-pin, 32-pin products]

• CSI: 1 channel/UART (UART supporting LIN-bus): 1 channel/simplified I2C: 1 channel

• CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel

[36-pin, 40-pin products]

• CSI: 1 channel/UART (UART supporting LIN-bus): 1 channel/simplified I2C: 1 channel

• CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel

• CSI: 2 channels/UART: 1 channel/simplified I2C: 2 channels

I2C bus

1 channel

Data transfer controller (DTC)

28 sources

29 sources

Event link controller (ELC)

Event input: 20

Event trigger output: 7

Vectored interrupt

sources

Internal

External

666

Key interrupt

———

Reset

• Reset by RESET pin

• Internal reset by watchdog timer

• Internal reset by power-on-reset

• Internal reset by voltage detector

• Internal reset by illegal instruction execution Note

• Internal reset by RAM parity error

• Internal reset by illegal-memory access

Power-on-reset circuit

• Power-on-reset:

1.51 ±0.03 V

• Power-down-reset:

1.50 ±0.03 V

Voltage detector

1.63 V to 4.06 V (14 stages)

On-chip debug function

Provided

Power supply voltage

VDD = 1.6 to 5.5 V

Operating ambient temperature

TA =

40 to +85 °C

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