L6717TR datasheet(52/56 Pages) STMICROELECTRONICS

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Layout guidelines

L6717

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Doc ID 17326 Rev 1

Layout guidelines

Layout is one of the most important things to consider when designing high current

applications. A good layout solution can generate a benefit in lowering power dissipation on

the power paths, reducing radiation and a proper connection between signal and power

ground can optimize the performance of the control loops.

Two kind of critical components and connections have to be considered when laying-out a

VRM based on L6717: power components and connections and small signal components

connections.

13.1

Power components and connections

These are the components and connections where switching and high continuous current

flows from the input to the load. The first priority when placing components has to be

reserved to this power section, minimizing the length of each connection and loop as much

as possible. To minimize noise and voltage spikes (EMI and losses) these interconnections

must be a part of a power plane and anyway realized by wide and thick copper traces: loop

must be anyway minimized. The critical components, i.e. the power transistors, must be

close one to the other. The use of multi-layer printed circuit board is recommended.

Traces between the driver section and the MOSFETs should be wide to minimize the

inductance of the trace so minimizing ringing in the driving signals. Moreover, VIAs count

needs to be minimized to reduce the related parasitic effect.

Locate the bypass capacitor (VCC, VCCDR and BOOT capacitors) close to the device with

the shortest possible loop and use wide copper traces to minimize parasitic inductance.

Systems that do not use Schottky diodes in parallel to the low-side MOSFET might show big

negative spikes on the phase pin. This spike can be limited as well as the positive spike but

it causes the bootstrap capacitor to be over-charged. This extra-charge can cause, in the

worst case condition of maximum input voltage and during particular transients, that boot-to-

phase voltage overcomes the abs.max.ratings also causing device failures. It is then

suggested in this cases to limit this extra-charge by adding a small resistor RBOOT in series

to the boot capacitor or the boot diode. The use of RBOOT also contributes in the limitation of

the spike present on the BOOT pin.

Figure 20.

Driver turn-on and turn-off paths

RGATE

RINT

CGD

CGS

CDS

VCCDR

LSx DRIVER

LS MOSFET

GND (PAD)

LGATEx

RGATE

RINT

CGD

CGS

CDS

BOOTx

HSx DRIVER

HS MOSFET

PHASEx

HGATEx

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