LTC1296CCSW datasheet(25/28 Pages) LINER

25 / 28 page

LTC1293/LTC1294/LTC1296

129346fs

Unipolar conversion is requested and the data is output

MSB first. CS is driven at 1/64 the clock rate by the CD4520

and DOUT outputs the data. The output data from the DOUT

pin can be viewed on an oscilloscope that is set up to

trigger on the falling edge of CS (Figure 24).

VERTICAL: 5V/DIV

HORIZONTAL: 2

µs/DIV

CLK

FILLS

ZEROES

LSB

(B0)

NULL

BIT

MSB

(B11)

Figure 24. Scope Trace of the

LTC1294/6 “Quick Look” Circuit

Showing A/D Output

101010101010 (AAAHEX)

LTC1293 TA03

µF

TANTALUM

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

COM

DGND

DVCC

AVCC

CLK

DOUT

DIN

REF+

REF–

AGND

V–

LTC1294

–

TO/FROM

68HC11

PROCESSOR

+15V

LT1006

30.1k**

µF

3.92M**

500k

ZERO

°C TRIM

+15V

–

LT1101

A=10

+15V

5VOUT

µF

500k

400

°C TRIM

12.5k*

12k*

1k*

Rplat.

* TRW-IRC MAR-6 RESISTOR – 0.1%

** 1% FILM RESISTOR

Rplat. = 1k

Ω AT 0°C – ROSEMOUNT #118MF

LT1027

Digitally Linearized Platinum RTD Signal Conditioner

OSCILLOSCOPE

LTC1293 F23

CLK

RESET

VSS

VDD

RESET

CLK

VIN

f/64

+5V

CLOCK IN

1MHz MAX

µF

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

COM

DGND

DVCC

AVCC

CLK

DOUT

DIN

REF+

REF–

AGND

V–

LTC1294

CD4520

Figure 23. “Quick Look” Circuit for the LTC1294/6

APPLICATI

TYPICAL

A “Quick Look” Circuit for the LTC1294/6

Users can get a quick look at the function and timing of the

LTC1294/6 by using the following simple circuit (Figure

23). VREF is tied to VCC. DIN is tied high which means VIN

should be applied to the CH7 with respect to COM. A

APPLICATI

I FOR ATIO

OUT

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