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IO130PDB3V2 Folha de dados(PDF) 25 Page - Microsemi Corporation |
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IO130PDB3V2 Folha de dados(HTML) 25 Page - Microsemi Corporation |
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25 / 212 page ![]() Military ProASIC3/EL Low Power Flash FPGAs Revision 3 2-11 Power per I/O Pin Table 2-13 • Summary of I/O Input Buffer Power (Per Pin) – Default I/O Software Settings Applicable to Pro I/Os for A3PE600L and A3PE3000L Only VCCI (V) Static Power PDC6 (mW)1 Dynamic Power PAC9 (µW/MHz)2 Single-Ended 3.3 V LVTTL/LVCMOS 3.3 – 16.34 3.3 V LVTTL/LVCMOS – Schmitt trigger 3.3 – 24.49 3.3 V LVCMOS Wide Range 3.3 – 16.34 3.3 V LVCMOS – Schmitt trigger Wide Range 3.3 – 24.49 2.5 V LVCMOS 2.5 – 4.71 2.5 V LVCMOS – Schmitt trigger 2.5 – 6.13 1.8 V LVCMOS 1.8 – 1.66 1.8 V LVCMOS – Schmitt trigger 1.8 – 1.78 1.5 V LVCMOS (JESD8-11) 1.5 – 1.01 1.5 V LVCMOS (JESD8-11) – Schmitt trigger 1.5 – 0.97 1.2 V LVCMOS 1.2 – 0.60 1.2 V LVCMOS (JESD8-11) – Schmitt trigger 1.2 – 0.53 1.2 V LVCMOS Wide Range 1.2 – 0.60 1.2 V LVCMOS Schmitt trigger Wide Range 1.2 – 0.53 3.3 V PCI 3.3 – 17.76 3.3 V PCI – Schmitt trigger 3.3 – 19.10 3.3 V PCI-X 3.3 – 17.76 3.3 V PCI-X – Schmitt trigger 3.3 – 19.10 Voltage-Referenced 3.3 V GTL 3.3 2.90 7.14 2.5 V GTL 2.5 2.13 3.54 3.3 V GTL+ 3.3 2.81 2.91 2.5 V GTL+ 2.5 2.57 2.61 HSTL (I) 1.5 0.17 0.79 HSTL (II) 1.5 0.17 0.79 SSTL2 (I) 2.5 1.38 3.26 SSTL2 (II) 2.5 1.38 3.26 SSTL3 (I) 3.3 3.21 7.97 SSTL3 (II) 3.3 3.21 7.97 Differential LVDS 2.5 2.26 0.89 LVPECL 3.3 5.71 1.94 Notes: 1. PDC6 is the static power (where applicable) measured on VCCI. 2. PAC9 is the total dynamic power measured on VCCI. |
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