WM8782

Production Data

w

PD, April 2010, Rev 4.7

10

SLAVE MODE MCLK / BCLK TIMING

BCLK

A

B

C

D

Keep-out area for MCLK/BCLK relationship

Figure 4 MCLK / BCLK prohibited timing relationship in slave mode

TIMING

TIME (ns)

DESCRIPTION

A

9

MCLK falling edge to BCLK falling edge keep-out window

B

4

C

9

MCLK rising edge to BCLK falling edge keep-out window

D

4

Table 4 Prohibited area timings

In slave mode operation, there are two windows where the BCLK falling edge relative to the MCLK

falling/rising edge is not allowed, as defined in Figure 4 and Table 4. Any device with clocks operating

in this area may cause incorrect operation of the ADC, as detailed in WTR0444.

This specification is guaranteed by design rather than test, and the timings are related to the

switching level of the MCLK and BCLK pads. Simulation has shown the switching level range for both

the MCLK and BCLK pads across process, voltage and temperature to be as per the table below.

SWITCHING LEVEL

MIN (V)

MAX (V)

1.1

1.4

1.3

1.6

Table 5 Simulated switching area range

If the above timing constraints cannot be met in slave mode, it is recommended that WM8782A

silicon is used in place of WM8782.