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OP177BZ Folha de dados(PDF) 3 Page - Analog Devices

Nome de Peças OP177BZ
Descrição Electrónicos  Ultraprecision Operational Amplifier
PDF  12 Pages
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Fabricante Electrônico  AD [Analog Devices]
Página de início  http://www.analog.com
Logo AD - Analog Devices

OP177BZ Folha de dados(HTML) 3 Page - Analog Devices

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OP177
REV. B
–3–
OP177E
OP177F
OP177G
Parameter
Symbol
Conditions
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Units
Input Offset Voltage
VOS
4
1010
2520
60
µV
Long-Term Input Offset
Voltage Stability
∆V
OS/Time
(Note 1)
0.2
0.3
0.4
µV/Mo
Input Offset Current
IOS
0.3
1.0
0.3
1.5
0.3
2.8
nA
Input Bias Current
IB
–0.2
1.0
1.5
–0.2
1.2
2.0
–0.2
1.2
2.8
nA
Input Noise Voltage
en
fo = 1 Hz to 100 Hz
2
118
150
118
150
118
150
nV rms
Input Noise Current
in
fo = 1 Hz to 100 Hz
2
3
8
38
38pA rms
Input Resistance
Differential-Mode
RIN
(Note 3)
26
45
26
45
18.5
45
M
Ω
Input Resistance
Common-Mode
RINCM
200
200
200
G
Ω
Input Voltage Range
IVR
(Note 4)
±13
±14
± 13
± 14
± 13
± 14
V
Common-Mode
Rejection Ratio
CMRR
VCM = ± 13 V
130
140
130
140
115
140
dB
Power Supply
Rejection Ratio
PSRR
VS = ±3 V to ± 18 V
120
125
115
125
110
120
dB
Large Signal
RL ≥ 2 kΩ,
Voltage Gain
AVO
VO = ± 10 V
5
5000
12000
5000
12000
2000
6000
V/mV
Output Voltage
Swing
VO
RL ≥ 10 kΩ± 13.5
±14.0
± 13.5 ± 14.0
± 13.5 ± 14.0
V
RL ≥ 2 kΩ± 12.5
±13.0
± 12.5 ± 13.0
± 12.5 ± 13.0
V
RL ≥ 1 kΩ± 12.0
±12.5
± 12.0 ± 12.5
± 12.0 ± 12.5
V
Slew Rate
SR
RL ≥ 2 kΩ
2
0.1
0.3
0.1
0.3
0.1
0.3
V/
µs
Closed-Loop
Bandwidth
BW
AVCL = +1
2
0.4
0.6
0.4
0.6
0.4
0.6
MHz
Open-Loop Output
Resistance
RO
60
60
60
Ω
Power Consumption
PD
VS = ± 15 V, No Load
50
60
50
60
50
60
mW
VS = ±3 V, No Load
3.5
4.5
3.5
4.5
3.5
4.5
mW
Supply Current
ISY
VS = ±15 V, No Load
1.6
2.0
1.6
2.0
1.6
2.0
mA
Offset Adjustment
Range
RP = 20 kΩ± 3
± 3
± 3mV
NOTES
1Long-Term Input Offset Voltage Stability refers to the averaged trend line of V
OS vs. time over extended periods after the first 30 days of operation. Excluding the ini-
tial hour of operation, changes in VOS during the first 30 operating days are typically less than 2.0 µV.
2Sample tested.
3Guaranteed by design.
4Guaranteed by CMRR test condition.
5To insure high open-loop gain throughout the
±10 V output range, A
VO is tested at –10 V ≤ VO ≤ 0 V, 0 V ≤ VO ≤ +10 V, and –10 V ≤ VO ≤ +10 V.
Specifications subject to change without notice.
ELECTRICAL CHARACTERISTICS (@ V
S =
15 V, TA = +25 C, unless otherwise noted)



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