REV. A

–12–

ADP3159/ADP3179

Efficiency of the Linear Regulators

The efficiency and corresponding power dissipation of each

of the linear regulators are not determined by the controller

IC. Rather, these are a function of input and output voltage and

load current. Efficiency is approximated by the formula:

η=

×

100%

V

V

OUT

IN

(34)

The corresponding power dissipation in the MOSFET, together

with any resistance added in series from input to output, is

given by:

PV

V

I

LDO

IN

OUT

OUT

=×

(

–

)

(35)

Minimum power dissipation and maximum efficiency are accom-

plished by choosing the lowest available input voltage that exceeds

the desired output voltage. However, if the chosen input source

is itself generated by a linear regulator, its power dissipation will

be increased in proportion to the additional current it must

now provide.

Implementing Current Limit for the Linear Regulators

The circuit of Figure 6 gives an example of a current limit pro-

tection circuit that can be used in conjunction with the linear

regulators. The output voltage is internally set by the LRFB pin.

The value of the current sense resistor may be calculated as

follows:

R

mV

I

mV

A

m

S

O MAX

≅==

Ω

540

540

22

250

()

.

(36)

The power rating of the current sense resistor must be at least:

PR

I

W

DRS

SO MAX

()

(

)

.

=×

=

2

12

(37)

The maximum linear regulator MOSFET junction temperature

with a shorted output is:

TT

V

I

TC

C W

V

A

C

MAX

A

C

IN

O MAX

MAX

JJ

J

()

()

()

()

(.

/

( .

.

)

=+

×

×

=° +

°

×

×

=°

θ

50

14

33

22

60

(38)

which is within the maximum allowed by the MOSFET’s data

sheet specification. The maximum MOSFET junction tempera-

ture at nominal output is:

TT

V

V

I

TC

C W

V

V

A

C

NOM

A

C

IN

OUT

O NOM

NOM

JJ

J

()

()

()

((

–

))

(.

/

( .

– .)

)

=+

×

×

=° +

°

×

×

=

°

θ

50

14

33

25

2

52

(39)

This example assumes an infinite heatsink. The practical limita-

tion will be based on the actual heatsink used.

LAYOUT AND COMPONENT PLACEMENT GUIDELINES

The following guidelines are recommended for optimal perfor-

mance of a switching regulator in a PC system:

General Recommendations

1.

For best results, a four-layer PCB is recommended. This

should allow the needed versatility for control circuitry

interconnections with optimal placement, a signal ground

plane, power planes for both power ground and the input

power (e.g., 5 V), and wide interconnection traces in the

rest of the power delivery current paths.

2.

Whenever high currents must be routed between PCB

layers, vias should be used liberally to create several parallel

current paths so that the resistance and inductance introduced

by these current paths is minimized and the via current

rating is not exceeded.

3.

If critical signal lines (including the voltage and current

sense lines of the controller IC) must cross through

power circuitry, it is best if a ground plane can be inter-

posed between those signal lines and the traces of the

power circuitry. This serves as a shield to minimize noise

injection into the signals at the cost of making signal

ground a bit noisier.

4.

The GND pin of the controller IC should connect first to

a ceramic bypass capacitor (on the VCC pin) and then into

the power ground plane. However, the ground plane should

not extend under other signal components, including the

ADP3159 itself.

5.

The output capacitors should also be connected as closely

as possible to the load (or connector) that receives the

power (e.g., a microprocessor core). If the load is distributed,

the capacitors should also be distributed, and generally in

proportion to where the load tends to be more dynamic. It

is also advised to keep the planar interconnection path short

(i.e., have input and output capacitors close together).

6.

Absolutely avoid crossing any signal lines over the switching

power path loop, described below.

Power Circuitry

7.

The switching power path should be routed on the PCB to

encompass the smallest possible area in order to minimize

radiated switching noise energy (i.e., EMI). Failure to take

proper precaution often results in EMI problems for the

entire PC system as well as noise-related operational prob-

lems in the power converter control circuitry. The switching

power path is the loop formed by the current path through

the input capacitors, the two FETs, and the power Schottky

diode, if used, including all interconnecting PCB traces and

planes. The use of short and wide interconnection traces is

especially critical in this path for two reasons: it minimizes

the inductance in the switching loop, which can cause high-

energy ringing, and it accommodates the high current demand

with minimal voltage loss.