REV. A

ADP3159/ADP3179

–11–

yield the proper voltage positioning gain, the dc biasing of that

resistor would determine how the regulation band is centered

(i.e., offset). Note that sometimes the specified regulation band

is asymmetrical with respect to the nominal VID voltage. With

the ADP3159, the offset is already considered part of the design

procedure—no special provision is required. To accomplish the

of these resistors can be calculated using:

R

V

gV

K

V

mmho

mV

k

A

DIV

m

OUT OS

=

×+

=

×+

×

=Ω

()

.

(

.

)

.

()

–

12

22

22

47 10

79 1

2

(26)

where K is a constant determined by internal characteristics of

the output voltage offset from the nominal VID-programmed

value under no load condition. This offset is given by Equation 30.

Ω. This value is then used

R

RR

RR

kk

kk

k

B

A

COMP

A

COMP

=

×

=

Ω×

Ω

ΩΩ

=Ω

–

..

.

– .

.

78 7

9 2

78 7

9 2

10 4

(27)

The nearest 1% value of 10.5 k

Ω was chosen for R

K

I

Rn

gR

V

gR

V

gR

K

Am

mmho

k

mmho

k

V

mmho

k

L RIPPLE

SENSE

I

m

TOTAL

GNL

m

TOTAL

CC

m

OGM

=×

×

×









+

××

=×

Ω×

×Ω









+

×Ω

−

××

Ω

=×

()

–

()

–

.

..

.

..

.

.

22

38

2

425

22

9 1

1 174

22

9 1

12

2

2 2

130

47 10

2

(28)

VV

IR

n

VV

L

tR

n

VV

Am

V

V

H

ns

m

V

GNL

GNLO

L RIPPLE

SENSE

I

IN

VID

D

SENSE

I

GNL

=+

××

−

−

××

×









=+

×Ω ×

−

µ

××

Ω ×









=

()

.

– .

.

.

2

1

38

4

25

2

51 7

15

75

4

25

1 174

(29)

VV

V

RI

Vk

VmV

mA

VmV

OUT OS

OUT MAX

VID

E MAX

L RIPPLE

VID

VID

OUT OS

()

(

)

()

(

)

()

–

.

.

=−

×

−×

=−

Ω×

−× ×

=

2

40

53 8

2

17

5 10

22

3

(30)

Finally, the compensating capacitance is determined from the

equality of the pole frequency of the error amplifier gain and the

zero frequency of the impedance of the output capacitor:

C

C

ESR

R

mF

m

k

nF

OC

OUT

TOTAL

=

×

=

×Ω

Ω

=

54 8

91

26

.

.

.

(31)

Trade-Offs Between DC Load Regulation and AC Load

Regulation

Casual observation of the circuit operation—e.g., with a voltmeter

—would make it appear that the dc load regulation appears to

be rather poor compared to a conventional regulator (see Figure

4). This would be especially noticeable under very light or very

heavy loads where the voltage is “positioned” near one of the

extremes of the regulation window rather than near the nominal

center value. It must be noted and understood that this low gain

characteristic (i.e., loose dc load regulation) is inherently required

to allow improved transient containment (i.e., to achieve tighter

ac load regulation). That is, the dc load regulation is intentionally

sacrificed (but kept within specification) in order to minimize

the number of capacitors required to contain the load transients

produced by the CPU.

68pF

2.5V

ADP3159/ADP3179

1k

250m

1 F

3.3V

100 F

2.5V, 2.2A

LRDRV1

LRFB1

10k

Figure 6. Adding Overcurrent Protection to the

Linear Regulator

Linear Regulators

The two linear regulators provide a low cost, convenient and

versatile solution for generating additional supply rails. The

maximum output load current is determined by the size and

thermal impedance of the external N-channel power MOSFET

that is placed in series with the supply. The output voltage is

sensed at the LRFB pin and compared to an internal reference

voltage in a negative feedback loop which keeps the output voltage

in regulation. If the load is reduced or increased, the MOSFET

drive will also be reduced or increased by the controller IC to

provide a well-regulated

±2.5% accurate output voltage.

The LRFB threshholds of the ADP3159 are internally set at

2.5 V(LRFB1) and 1.8 V(LRFB2), while the LRFB pins of the

ADP3179 are compared to an internal 1 V reference. This allows

the use of an external resistor divider network to program the

linear regulator output voltage. The correct resistor values for

setting the output voltage of the linear regulators in the

ADP3179 can be determined using:

VV

RR

R

OUT(LR)

LRFB

UL

L

=×

+

(32)

R

10 k

V

V

V

R

10 k

1.2V

1V

1V

2k

U

OUT(LR)

LRFB

LRFB

U

=

Ω×

−

()

=

Ω×

−

()

=Ω

(33)