AD9761ARS datasheet(11/23 Pages) AD

11 / 23 page

AD9761

–11–

REV. A

Referring to Figure 23, the “new” first image associated with the

DAC’s higher data rate after interpolation is “pushed” out fur-

ther relative to the input signal. The “old” first image associated

with the lower DAC data rate before interpolation is suppressed

by the digital filter. As a result, the transition band for the ana-

log reconstruction filter is increased thus reducing the complex-

ity of the analog filter.

The digital interpolation filters for I and Q paths are identical

43 tap halfband symmetric FIR filters. Each filter receives de-

interleaved I or Q data from the digital input interface. The

input CLOCK signal is internally divided by two to generate the

filter clock. The filters are implemented with two parallel paths

running at the filter clock rate. The output from each path is

selected on opposite phases of the filter clock, thus producing

interpolated filtered output data at the input clock rate. The

frequency response and impulse response of these filters are

shown in Figures 2a and 2b. Table I lists the idealized filter

coefficients that correspond to the filter’s impulse response.

The digital section of the AD9761 also includes an input inter-

face section designed to support interleaved I and Q input data

from a single 10-bit bus. This section de-interleaves the I and Q

input data while ensuring its proper pairing for the 2

× interpola-

tion filters. A SLEEP/RESET input serves a dual function by

providing a reset function for this section as well as providing

power down functionality. Refer to the DIGITAL INPUT AND

INTERFACE CONSIDERATIONS and SLEEP/RESET

sections for a more detailed discussion.

DAC TRANSFER FUNCTION

Each I and Q DAC provides complementary current output

pins: IOUT(A/B) and QOUT(A/B) respectively. Note, QOUTA

and QOUTB operate identically to IOUTA and IOUTB.

IOUTA will provide a near full-scale current output, IOUTFS,

when all bits are high (i.e., DAC CODE = 1023) while IOUTB,

the complementary output, provides no current. The current

output of IOUTA and IOUTB are a function of both the input

code and IOUTFS and can be expressed as:

IIOUTA = (DAC CODE/1024)

× I

OUTFS

(1)

IIOUTB = (1023 – DAC CODE)/1024

× I

OUTFS

(2)

where:

DAC CODE = 0 to 1023 (i.e., Decimal Representation).

As previously mentioned, IOUTFS is a function of the reference

current, IREF, which is nominally set by a reference, VREFIO, and

external resistor, RSET. It can be expressed as:

IOUTFS = 16

× I

REF

(3)

where:

IREF = VREFIO/RSET

(4)

The two current outputs will typically drive a resistive load

directly or via a transformer. If dc coupling is required, IOUTA

and IOUTB should be directly connected to matching resistive

loads, RLOAD, which are tied to analog common, ACOM. Note,

RLOAD represents the equivalent load resistance seen by IOUTA

or IOUTB. The single-ended voltage output appearing at IOUTA

and IOUTB pins is simply:

VIOUTA = IIOUTA

× R

LOAD

(5)

VIOUTB = IIOUTB

× R

LOAD

(6)

Note, the full-scale value of VIOUTA and VIOUTB should not

exceed the specified output compliance range to maintain speci-

fied distortion and linearity performance.

The differential voltage, VIDIFF, appearing across IOUTA and

IOUTB is:

VIDIFF =(IIOUTA – IIOUTB)

× R

LOAD

(7)

Substituting the values of IIOUTA, IIOUTB, and IREF; VIDIFF can be

expressed as:

VIDIFF ={(2 DAC CODE – 1023)/1024)}

(16 RLOAD/RSET)

× V

REFIO

(8)

These last two equations highlight some of the advantages of

operating the AD9761 differentially. First, differential operation

will help cancel common-mode error sources associated with

IIOUTA and IIOUTB such as noise and distortion. Second, the

differential code dependent current and subsequent voltage,

VIDIFF, is twice the value of the single-ended voltage output (i.e.,

VIOUTA or VIOUTB) thus providing twice the signal power to the

load.

REFERENCE OPERATION

The AD9761 contains an internal 1.20 V bandgap reference

which can be easily disabled and overridden by an external

reference. REFIO serves as either an input or output depending

on whether the internal or an external reference is selected. If

REFLO is tied to ACOM as shown in Figure 24, the internal

reference is activated and REFIO provides a 1.20 V output. In

this case, the internal reference must be filtered externally with a

ceramic chip capacitor of 0.1

µF or greater from REFIO to

REFLO. Also, REFIO should be buffered with an external

amplifier having a low input bias current (i.e., <1

µA) if any

additional loading is required.

50pF

CURRENT

SOURCE

ARRAY

+1.2V REF

REFIO

FSADJ

REFLO

COMP2

AVDD

0.1 F

RSET

0.1 F

OPTIONAL EXTERNAL

REF BUFFER FOR

ADDITIONAL LOADS

COMPENSATION

CAPACITOR

REQUIRED

AD9761

Figure 24. Internal Reference Configuration

The internal reference can also be disabled by connecting REFLO

to AVDD. In this case, an external reference may then be ap-

plied to REFIO as shown in Figure 25. The external reference

may provide either a fixed reference voltage to enhance accuracy

and drift performance or a varying reference voltage for gain

control. Note that the 0.1

µF compensation capacitor is not

required since the internal reference is disabled and the high

input impedance (i.e., 1 M

Ω) of REFIO minimizes any loading

of the external reference.

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