AD9761ARS datasheet(6/23 Pages) AD

6 / 23 page

AD9761

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REV. A

PIN FUNCTION DESCRIPTIONS

Pin No.

Name

Description

DB9

Most Significant Data Bit (MSB).

2–9

DB8–DB1

Data Bits 1-8.

DB0

Least Significant Data Bit (LSB).

CLOCK

Clock Input. Both DACs’ outputs updated on positive edge of clock and digital filters read respective

input registers.

WRITE

Write input. DAC input registers latched on positive edge of write.

SELECT

Select Input. Select high routes input data to I DAC, select low routes data to Q DAC.

DVDD

Digital Supply Voltage (+2.7 V to +5.5 V).

DCOM

Digital Common.

COMP3

Internal Bias Node for Switch Driver Circuitry. Decouple to ACOM with 0.1

µF capacitor.

QOUTA

Q DAC Current Output. Full-scale current when all data bits are 1s.

QOUTB

Q DAC Complementary Current Output. Full-scale current when all data bits are 0s.

REFLO

Reference Ground when Internal 1.2 V Reference Used. Connect to AVDD to disable internal

reference.

REFIO

Reference Input/Output. Serves as reference input when internal reference disabled. Serves as 1.2 V

reference output when internal reference activated. Requires 0.1

µF capacitor to ACOM when inter-

nal reference activated.

FSADJ

Full-Scale Current Output Adjust. Resistance to ACOM sets full-scale output current.

COMP2

Bandwidth/Noise Reduction Node. Add 0.1

µF to AVDD for optimum performance.

AVDD

Analog Supply Voltage (+2.7 V to +5.5 V).

ACOM

Analog Common.

IOUTB

I DAC Complementary Current Output. Full-scale current when all data bits are 0s.

IOUTA

I DAC Current Output. Full-scale current when all data bits are 1s.

COMP1

Internal Bias Node for Switch Driver Circuitry. Decouple to AGND with 0.1

µF capacitor.

RESET/SLEEP

Power-Down control input if asserted for four clock cycles or longer. Reset control input if asserted

for less than four clock cycles. Active high. Connect to DCOM if not used. Refer to RESET/SLEEP

section.

PIN CONFIGURATION

TOP VIEW

(Not to Scale)