AD7875LP datasheet(14/20 Pages) AD

14 / 20 page

REV. B

AD7870/AD7875/AD7876

–14–

Serial Interfacing

Figures 21 to 24 show the AD7870/AD7875/AD7876 config-

ured for serial interfacing. In all four interfaces, the ADC is con-

figured for Mode 1 operation. The interfaces show a timer

driving the

CONVST input, but this could be generated from a

decoded address if required. The SCLK, SDAT and

SSTRB are

open-drain outputs. If these are required to drive capacitive

loads in excess 35 pF, buffering is recommended.

DSP56000 Serial Interface

Figure 21 shows a serial interface between the AD7870/

AD7875/AD7876 and the DSP56000. The interface arrange-

ment is two-wire with the ADC configured for noncontinuous

clock operation (12/

8/CLK = 0 V). The DSP56000 is config-

ured for normal mode asynchronous operation with gated clock.

It is also set up for a 16-bit word with SCK and SC1 as inputs

and the FSL control bit set to a 0. In this configuration, the

DSP56000 assumes valid data on the first falling edge of SCK.

Since the ADC provides valid data on this first edge, there is no

need for a strobe or framing pulse for the data. SCLK and

SDATA are gated off when the ADC is not performing a con-

version. During conversion, data is valid on the SDATA output

of the ADC and is clocked into the receive data shift register of

the DSP56000. When this register has received 16 bits of data,

it generates an internal interrupt on the DSP56000 to read the

data from the register.

Figure 21. DSP56000 Serial Interface

The DSP56000 and AD7870/AD7875/AD7876 can also be

configured for continuous clock operation (12/

8/CLK = –5 V).

In this case, a strobe pulse is required by the DSP56000 to indi-

cate when data is valid. The

SSTRB output of the ADC is in-

verted and applied to the SC1 input of the DSP56000 to

provide this strobe pulse. All other conditions and connections

are the same as for gated clock operation.

NEC7720/77230 Serial Interface

A serial interface between the AD7870/AD7875/AD7876 and

the NEC7720 is shown in Figure 22. In the interface shown, the

ADC is configured for continuous clock operation. This can be

changed to a noncontinuous clock by simply tying the 12/

8/CLK

input of the ADC to 0 V with all other connections remaining

the same. The NEC7720 expects valid data on the rising edge of

its SCK input and therefore an inverter is required on the

SCLK output of the ADC. The NEC7720 is configured for a

16-bit data word. Once the 16 bits of data have been received

by the SI register of the NEC7720, an internal interrupt is gen-

erated to read the contents of the SI register.

The NEC77230 interface is similar to that just outlined for the

NEC7720. However, the clock input of the NEC77230 is

SICLK. Additionally, no inverter is required between the ADC

SCLK output and this SICLK input since the NEC77230 as-

sumes data is valid on the falling edge of SICLK.

Figure 22. NEC7720 Serial Interface

TMS32020 Serial Interface

Figure 23 shows a serial interface between the AD7870/ AD7875/

AD7876 and the TMS32020. The AD7870/AD7875/AD7876 is

configured for continuous clock operation. Note, the ADC will

not interface correctly to the TMS32020 if the ADC is config-

ured for a noncontinuous clock. Data is clocked into the data

receive register (DRR) of the TMS32020 during conversion. As

with the previous interfaces, when a 16-bit word is received by

the TMS32020 it generates an internal interrupt to read the

data from the DRR.

Figure 23. TMS32020 Serial Interface

ADSP-2101/ADSP-2102 Serial Interface

Figure 24 shows a serial interface between the AD7870/AD7875/

AD7876 and the ADSP-2101/ADSP-2102. The ADC is config-

ured for continuous clock operation. Data is clocked into the

serial port register of the ADSP-2101/ADSP-2102 during con-

version. As with the previous interfaces, when a 16-bit data

word is received by the ADSP-2101/ADSP-2102 an internal mi-

croprocessor interrupt is generated and the data is read from the

serial port register.

Figure 24. ADSP-2101/ADSP-2102 Serial Interface

AD7875LP Folha de dados(PDF) 14 Page - Analog Devices

AD7875LP Folha de dados(HTML) 14 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

Folha de dados Download

Ligação URL