Triple Output Step-Down Switching Regulator

A4491

8

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

voltage is falling. Note that this feature is only guaranteed when

VDD is supplied externally. During this interval, the three switch-

ers continue to operate.

degrades the drive voltage to the series switches. In addition,

the higher voltage rails start to fall out of regulation first, as the

converters is reached.

The regulators that have the lower output voltages achieve some

level of steady state, before the A4491 powers down when all

reached. For example, it may be possible for a 1 V output to

supply is derived externally. The extent of this effect depends on

a myriad of factors, including input and output filter capacitance,

forth.

Powering Up and Down with Enable Referring to figure 2,

enabled in turn. Initially, VREG1 is enabled and is brought-up

reaches 85% FB1, VREG2 is enabled and is brought-up under a

separate soft start control.

When both regulators have reached their respective 85% FB

thresholds, the power-on-reset (POR) timer is initiated. Note that

the POR timer is only enabled after all of the enabled regulators

reach their corresponding 85% FB levels. After the power-on-

VREG2 are not below their respective 80% FB levels, then the

PORZ signal will go high.

At some point later, if VREG3 is enabled, then the PORZ is

reset and VREG3 is brought-up under the control of the soft start

circuit. When the 85% FB3 threshold is reached, the POR timer

their respective 80% FB levels, then the PORZ signal will go

high.

Note that if any regulator channel is not enabled, the channel

will not influence PORZ. To avoid multiple signal changes of the

PORZ signal, it is recommended that the system be designed such

that all three regulator channels are within specification before

If any regulator channel drops below 80% FB, the PORZ signal

will be reset. If the voltage then recovers to within 85% FB, the

POR timer is initiated again. Note that a soft start is not initiated

when the feedback voltage drops below the 80% FB level. This is

to allow a rapid auto-restart in the event of an overload or similar

fault. If a soft start is required, it is recommended that on receipt

of the PORZ reset signal, the system controller disables and then

re-enables the relevant regulator channels again. As soon as the

last regulator is disabled the PORZ signal is reset.

mined by selecting an appropriate capacitor connected to the

formula:

(1)

voltage warning levels, and the FB pins of the regulators that are

Because the external capacitor is charged via a 5 μA current

source, care must be taken in the layout to avoid additional leak-

age paths. The capacitor should be positioned adjacent to the

CPOR pin, and the ground connection to the A4491 GND pin

should be as short as possible.

start-up phases of all three regulators, to avoid the possibility of

multiple triggerings of the PORZ output.

Output Voltage Selection The output voltage on each of the

three regulators is set by the following relationship, shown here

for the VREG1 channel:

=,

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

– 1

(2)

where R2 (connected between GND and the FB1 pin) should

be a value between 4.7 and 12 kΩ. R1 is connected between the

The tolerances of the feedback resistors influence the voltage set-

point. It is therefore important to consider the tolerance selection

when targeting an overall regulation figure.