SPC56AP54X datasheet(14/104 Pages) STMICROELECTRONICS

14 / 104 page

Introduction

SPC56xP54x, SPC56xP60x

14/104

Doc ID 18340 Rev 3

The crossbar provides the following features:

●

6 master ports:

–

2 e200z0 core complex Instruction ports

–

2 e200z0 core complex Load/Store Data ports

–eDMA

–FlexRay

●

6 slave ports:

–

2 Flash memory (code flash and data flash)

–

2 SRAM (48 KB + 32 KB)

–

2 PBRIDGE

●

32-bit internal address, 32-bit internal data paths

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Fixed Priority Arbitration based on Port Master

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Temporary dynamic priority elevation of masters

1.5.3

Enhanced direct memory access (eDMA)

The enhanced direct memory access (eDMA) controller is a second-generation module

capable of performing complex data movements via 16 programmable channels, with

minimal intervention from the host processor. The hardware micro architecture includes a

DMA engine which performs source and destination address calculations, and the actual

data movement operations, along with an SRAM-based memory containing the transfer

control descriptors (TCD) for the channels. This implementation is utilized to minimize the

overall block size.

The eDMA module provides the following features:

●

16 channels support independent 8, 16 or 32-bit single value or block transfers

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Supports variable sized queues and circular queues

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Source and destination address registers are independently configured to post-

increment or remain constant

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Each transfer is initiated by a peripheral, CPU, or eDMA channel request

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Each eDMA channel can optionally send an interrupt request to the CPU on completion

of a single value or block transfer

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DMA transfers possible between system memories, DSPIs, ADC, eTimer and CTU

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Programmable DMA Channel Multiplexer for assignment of any DMA source to any

available DMA channel with up to 30 potential request sources

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eDMA abort operation through software

1.5.4

On-chip flash memory with ECC

The SPC56xP54/60 provides up to 1024 KB of programmable, non-volatile, flash memory.

The non-volatile memory (NVM) can be used for instruction and/or data storage. The flash

memory module interfaces the system bus to a dedicated flash memory array controller. It

supports a 32-bit data bus width at the system bus port, and a 128-bit read data interface to

flash memory. The module contains a four-entry, 4x128-bit prefetch buffers. Prefetch buffer

hits allow no-wait responses. Normal flash memory array accesses are registered and are

forwarded to the system bus on the following cycle, incurring 2 wait states.

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