SPC56AP54X datasheet(12/104 Pages) STMICROELECTRONICS

12 / 104 page

Introduction

SPC56xP54x, SPC56xP60x

12/104

Doc ID 18340 Rev 3

Peripheral bridge (PBRIDGE)

Is the interface between the system bus and on-chip peripherals

Periodic interrupt timer (PIT)

Produces periodic interrupts and triggers

Power control unit (MC_PCU)

Reduces the overall power consumption by disconnecting parts of the device

from the power supply via a power switching device; device components are

grouped into sections called “power domains” which are controlled by the PCU

Reset generation module

(MC_RGM)

Centralizes reset sources and manages the device reset sequence of the

device

Semaphore unit (SEMA4)

Provides the hardware support needed in multi-core systems for implementing

semaphores and provide a simple mechanism to achieve lock/unlock

operations via a single write access

Static random-access memory

(SRAM)

Provides storage for program code, constants, and variables

System integration unit lite (SIUL)

Provides control over all the electrical pad controls and up 32 ports with 16 bits

of bidirectional, general-purpose input and output signals and supports up to 32

external interrupts with trigger event configuration

System status and configuration

module (SSCM)

Provides system configuration and status data (such as memory size and

status, device mode and security status), device identification data, debug

status port enable and selection, and bus and peripheral abort enable/disable

System timer module (STM)

Provides a set of output compare events to support AUTOSAR(1) and operating

system tasks

System watchdog timer (SWT)

Provides protection from runaway code

Wakeup unit (WKPU)

Supports up to 18 external sources that can generate interrupts or wakeup

events, of which 1 can cause non-maskable interrupt requests or wakeup

events.

AUTOSAR: AUTomotive Open System ARchitecture (see www.autosar.org)

Table 4.

SPC56xP54/60 series block summary (continued)

Block

Function

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