C6416 datasheet(92/134 Pages) TI1

92 / 134 page

SMJ320C6414, SMJ320C6415, SMJ320C6416

FIXEDPOINT DIGITAL SIGNAL PROCESSORS

SGUS050A − JANUARY 2004 − REVISED MARCH 2004

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

PROGRAMMABLE SYNCHRONOUS INTERFACE TIMING (CONTINUED)

ECLKOUTx

CEx

ABE[7:0] or BBE[1:0]

AEA[22:3] or BEA[20:1]

AED[63:0] or BED[15:0]

ARE/SDCAS/SADS/SRE¶

AOE/SDRAS/SOE¶

AWE/SDWE/SWE¶

BE1

BE2

BE3

BE4

EA1

EA2

EA3

EA4

Write

Latency =

1‡

† These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a

“B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the programmable

synchronous interface access signals are shown as generic (SADS/SRE, SOE, and SWE) instead of ASADS/ASRE, ASOE, and ASWE (for

EMIFA) and BSADS/BSRE, BSOE, and BSWE (for EMIFB)].

‡ The write latency and the length of CEx assertion are programmable via the SYNCWL and CEEXT fields, respectively, in the EMIFx CE Space

Secondary Control register (CExSEC). In this figure, SYNCWL = 1 and CEEXT = 0.

§ The following parameters are programmable via the EMIF CE Space Secondary Control register (CExSEC):

− Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency

− Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency

− CEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, CEx goes inactive after the final command has been issued

(CEEXT = 0). For synchronous FIFO interface with glue, CEx is active when SOE is active (CEEXT = 1).

− Function of SADS/SRE (RENEN): For standard SBSRAM or ZBT SRAM interface, SADS/SRE acts as SADS with deselect cycles

(RENEN = 0). For FIFO interface, SADS/SRE acts as SRE with NO deselect cycles (RENEN = 1).

− Synchronization clock (SNCCLK): Synchronized to ECLKOUT1 or ECLKOUT2

¶ ARE/SDCAS/SADS/SRE, AOE/SDRAS/SOE, and AWE/SDWE/SWE operate as SADS/SRE, SOE, and SWE, respectively, during

programmable synchronous interface accesses.

Figure 26. Programmable Synchronous Interface Write Timing for EMIFA and EMIFB

(With Write Latency = 1)†‡§

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