C6416 datasheet(69/134 Pages) TI1

69 / 134 page

SMJ320C6414, SMJ320C6415, SMJ320C6416

FIXEDPOINT DIGITAL SIGNAL PROCESSORS

SGUS050A − JANUARY 2004 − REVISED MARCH 2004

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

clock PLL (continued)

Table 32. SMJ320C64x PLL Multiply Factor Options, Clock Frequency Ranges, and Typical Lock Time†‡

GAD PACKAGE − Micro Pin PGA

CLKMODE1

CLKMODE0

CLKMODE

(PLL MULTIPLY

FACTORS)

CLKIN

RANGE

(MHz)

CPU CLOCK

FREQUENCY

RANGE (MHz)

CLKOUT4

RANGE (MHz)

CLKOUT6

RANGE (MHz)

TYPICAL

LOCK TIME

(

µs)§

Bypass (x1)

30−75

7.5−18.8

5−12.5

N/A

30−75

180−450

45−112.5

30−75

x12

30−60

360−720

90−180

60−120

Reserved

−

† These clock frequency range values are applicable to a C64x−60 speed device..

‡ Use external pullup resistors on the CLKMODE pins (CLKMODE1 and CLKMODE0) to set the C64x device to one of the valid PLL multiply clock

modes (x6 or x12). With internal pulldown resistors on the CLKMODE pins (CLKMODE1, CLKMODE0), the default clock mode is x1 (bypass).

§ Under some operating conditions, the maximum PLL lock time may vary by as much as 150% from the specified typical value. For example, if

the typical lock time is specified as 100

µs, the maximum value may be as long as 250 µs.

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