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Os motores de busca de Datasheet de Componentes eletrônicos |
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Os motores de busca de Datasheet de Componentes eletrônicos |
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LTM9012 Folha de dados(PDF) 5 Page - Linear Technology |
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LTM9012 Folha de dados(HTML) 5 Page - Linear Technology |
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5 / 28 page  LTM9012 5 9012f power requireMenTs The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 6) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VDD ADC Supply Voltage (Note 10) l 1.7 1.8 1.9 V OVDD ADC Output Supply Voltage (Note 10) l 1.7 1.8 1.9 V VCC Amplifier Supply Voltage (Note 10) l 2.7 3.3 3.6 V IVDD ADC Supply Current Sine Wave Input l 298 320 mA IOVDD ADC Output Supply Current 2-Lane Mode, 1.75mA Mode 2-Lane Mode, 3.5mA Mode l l 27 49 31 54 mA mA IVCC Amplifier Supply Current l 208 224 mA PDISS 2-Lane Mode, 1.75mA Mode 2-Lane Mode, 3.5mA Mode l l 1271 1311 1473 1517 mW mW PSLEEP 3 mW PNAP 85 mW PDIFFCLK Power Decrease with Single-Ended Encode Mode Enabled 20 mW TiMing characTerisTics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 6) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS fS Sampling Frequency (Note 10, Note 11) l 5 125 MHz tENCL ENC Low Time (Note 9) Duty Cycle Stabilizer Off Duty Cycle Stabilizer On l l 3.8 2 4 4 100 100 ns ns tENCH ENC High Time (Note 9) Duty Cycle Stabilizer Off Duty Cycle Stabilizer On l l 3.8 2 4 4 100 100 ns ns tAP Sample-and-Hold Acquisition Delay Time 0 ns Digital Data Outputs (RTERM = 100Ω Differential, CL = 2pF to GND on Each Output) tSER Serial Data Bit Period 2-Lanes, 16-Bit Serialization 2-Lanes, 14-Bit Serialization 2-Lanes, 12-Bit Serialization 1-Lane, 16-Bit Serialization 1-Lane, 14-Bit Serialization 1-Lane, 12-Bit Serialization 1/(8•fS) 1/(7•fS) 1/(6•fS) 1/(16•fS) 1/(14•fS) 1/(12•fS) sec sec sec sec sec sec tFRAME FR to DCO Delay (Note 9) l 0.35•tSER 0.5•tSER 0.65•tSER sec tDATA DATA to DCO Delay (Note 9) l 0.35•tSER 0.5•tSER 0.65•tSER sec tPD Propagation Delay (Note 9) l 0.7n + 2•tSER 1.1n + 2•tSER 1.5n + 2•tSER sec tR Output Rise Time Data, DCO, FR, 20% to 80% 0.17 ns tF Output Fall Time Data, DCO, FR, 20% to 80% 0.17 ns DCO Cycle-Cycle Jitter tSER = 1ns 60 psP-P Pipeline Latency 6 Cycles SPI Port Timing (Note 9) tSCK SCK Period Write Mode Read Back Mode, CSDO = 20pF, RPULLUP = 2k l l 40 250 ns ns tS CS to SCK Setup Time l 5 ns tH SCK to CS Setup Time l 5 ns tDS SDI Setup Time l 5 ns tDH SDI Hold Time l 5 ns tDO SCK Falling to SDO Valid Read Back Mode, CSDO = 20pF, RPULLUP = 2k l 125 ns |
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