LTM9012 datasheet(18/28 Pages) LINER

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LTM9012

9012f

applicaTions inForMaTion

Sleep and Nap Modes

The A/D may be placed in sleep or nap modes to conserve

power. In sleep mode the entire chip is powered down, re-

sultingin3mWpowerconsumption.Sleepmodeisenabled

by mode control register A1 (serial programming mode),

or by SDI (parallel programming mode). The amount of

time required to recover from sleep mode depends on the

size of the bypass capacitors on VREF, REFH, and REFL.

For the internal capacitor values and no additional external

capacitance, the A/D will stabilize after 2ms.

In nap mode any combination of A/D channels can be

powered down while the internal reference circuits and the

PLL stay active, allowing faster wakeup than from sleep

mode. Recovering from nap mode requires at least 100

clock cycles. If the application demands very accurate DC

settling then an additional 50μs should be allowed so the

on-chip references can settle from the slight temperature

shift caused by the change in supply current as the A/D

leaves nap mode. Nap mode is enabled by mode control

Driver Amplifier Shutdown (SHDN)

The ADC drivers may be placed in shutdown mode to

conserve power independently from the ADC core. Each

ADC driver has an independent SHDN pin but it is expected

that all four will be tied together.

DEVICE PROGRAMMING MODES

The operating modes of the LTM9012 can be programmed

by either a parallel interface or a simple serial interface.

The serial interface has more flexibility and can program

all available modes. The parallel interface is more limited

and can only program some of the more commonly used

modes.

Parallel Programming Mode

To use the parallel programming mode, PAR/SER should

be tied to VDD. The CS, SCK, SDI and SDO pins are binary

logic inputs that set certain operating modes. These pins

can be tied to VDD or ground, or driven by 1.8V, 2.5V, or

3.3V CMOS logic. When used as an input, SDO should

be driven through a 1k series resistor. Table 3 shows the

modes set by CS, SCK, SDI and SDO.

Table 3. Parallel Programming Mode Control Bits

(PAR/SER = VDD)

DESCRIPTION

2-Lane/1-Lane Selection Bit

0 = 2-Lane, 16-Bit Serialization Output Mode

1 = 1-Lane, 14-Bit Serialization Output Mode

SCK

LVDS Current Selection Bit

0 = 3.5mA LVDS Current Mode

1 = 1.75mA LVDS Current Mode

SDI

Power Down Control Bit

0 = Normal Operation

1 = Sleep Mode

SDO

Internal Termination Selection Bit

0 = Internal Termination Disabled

1 = Internal Termination Enabled

Serial Programming Mode

To use the serial programming mode, PAR/SER should be

tied to ground. The CS, SCK, SDI and SDO pins become a

serialinterfacethatprogramtheA/Dmodecontrolregisters.

Data is written to a register with a 16-bit serial word. Data

can also be read back from a register to verify its contents.

Serial data transfer starts when CS is taken low. The data

on the SDI pin is latched at the first 16 rising edges of

SCK. Any SCK rising edges after the first 16 are ignored.

The data transfer ends when CS is taken high again.

The first bit of the 16-bit input word is the R/W bit. The

next seven bits are the address of the register (A6:A0).

The final eight bits are the register data (D7:D0).

If the R/W bit is low, the serial data (D7:D0) will be writ-

ten to the register set by the address bits (A6:A0). If the

R/W bit is high, data in the register set by the address bits

(A6:A0) will be read back on the SDO pin (see the Timing

Diagrams sections). During a read back command the

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