© 2009 Fairchild Semiconductor Corporation

www.fairchildsemi.com

FSEZ1016A • Rev. 1.0.2

15

Physical Dimensions

8°

0°

SEE DETAIL A

NOTES:

A) THIS PACKAGE CONFORMS TO JEDEC

MS-012 VARIATION AA EXCEPT FOR MISSING PIN 7.

B) ALL DIMENSIONS ARE IN MILLIMETERS.

C) DIMENSIONS DO NOT INCLUDE MOLD

FLASH OR BURRS.

D) DRAWING FILENAME: M07AREV2

LAND PATTERN RECOMMENDATION

SEATING PLANE

0.10 C

C

GAGE PLANE

x 45°

DETAIL A

SCALE: 2:1

PIN ONE

INDICATOR

4

8

1

C

M

BA

0.25

B

5

A

5.60

0.65

1.75

1.27

6.20

5.80

3.81

4.00

3.80

5.00

4.80

(0.33)

1.27

0.51

0.33

0.25

0.10

1.75 MAX

0.25

0.19

0.36

0.50

0.25

R0.10

R0.10

0.90

0.406

(1.04)

OPTION A - BEVEL EDGE

OPTION B - NO BEVEL EDGE

Figure 33.

7-Lead, Small-Outline Integrated Circuit Package (SOIC)

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