MPC8358E datasheet(2/95 Pages) FREESCALE

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MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3

Freescale Semiconductor

Overview

1Overview

This section describes a high-level overview including features and general operation of the MPC8358E

PowerQUICC II Pro processor. A major component of this device is the e300 core, which includes

32 Kbytes of instruction and data cache and is fully compatible with the Power Architecture™ 603e

instruction set. The new QUICC Engine module provides termination, interworking, and switching

between a wide range of protocols including ATM, Ethernet, HDLC, and POS. The QUICC Engine

module’s enhanced interworking eases the transition and reduces investment costs from ATM to IP based

systems. The MPC8358E has a single DDR SDRAM memory controller. The MPC8358E also offers a

32-bit PCI controller, a flexible local bus, and a dedicated security engine.

Figure 1 shows the MPC8358E block diagram.

Figure 1. MPC8358E Block Diagram

Major features of the MPC8358E are as follows:

•

e300 PowerPC processor core (enhanced version of the MPC603e core)

— Operates at up to 400 MHz (for the MPC8358E)

— High-performance, superscalar processor core

— Floating-point, integer, load/store, system register, and branch processing units

Memory Controllers

GPCM/UPM/SDRAM

32/64 DDR Interface Unit

PCI Bridge

Local Bus

Bus Arbitration

DUART

Dual I2C

4 Channel DMA

Interrupt Controller

Protection & Configuration

System Reset

Clock Synthesizer

System Interface Unit

(SIU)

Local

Baud Rate

Generators

Multi-User

RAM

Parallel I/O

Accelerators

Dual 32-Bit RISC CP

Serial DMA

2 Virtual

DMAs

2 GMII/

RGMII/TBI/RTBI

6 MII/

RMII

4 TDM Ports

1 UTOPIA/POS

(31/124 MPHY)

Serial Interface

QUICC Engine Module

JTAG/COP

Power

Management

Timers

FPU

Classic G2 MMUs

32KB

D-Cache

32KB

I-Cache

Security Engine

e300 Core

PCI

DDRC

Time Slot Assigner

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