MPC8358E datasheet(4/95 Pages) FREESCALE

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MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3

Freescale Semiconductor

Overview

– ATM (AAL2/AAL5) to Ethernet (IP) interworking in accordance with RFC2684 including

bridging of ATM ports to Ethernet ports

– Extensive support for ATM statistics and Ethernet RMON/MIB statistics

– AAL2 protocol rate up to 4 CPS at OC-3/STM-1 rate

– Packet over Sonet (POS) up to 622-Mbps full-duplex 124 MultiPHY

– POS hardware; microcode must be loaded as an IRAM package

– Transparent up to 70-Mbps full-duplex

– HDLC up to 70-Mbps full-duplex

– HDLC BUS up to 10 Mbps

– Asynchronous HDLC

– UART

– BISYNC up to 2 Mbps

– User-programmable Virtual FIFO size

– QUICC multichannel controller (QMC) for 64 TDM channels

— One UTOPIA/POS interface on the MPC8358E supporting 31/124 MultiPHY

— Two serial peripheral interfaces (SPI); SPI2 is dedicated to Ethernet PHY management

— Four TDM interfaces on the MPC8358E with 1-bit mode for E3/T3 rates in clear channel

— Sixteen independent baud rate generators and 30 input clock pins for supplying clocks to UCC

serial channels

— Four independent 16-bit timers that can be interconnected as four 32-bit timers

— Interworking functionality:

– Layer 2 10/100-Base T Ethernet switch

– ATM-to-ATM switching (AAL0, 2, 5)

– Ethernet-to-ATM switching with L3/L4 support

– PPP interworking

•

Security engine is optimized to handle all the algorithms associated with IPSec, SSL/TLS, SRTP,

802.11i®, iSCSI, and IKE processing. The security engine contains four crypto-channels, a

controller, and a set of crypto execution units (EUs).

— Public key execution unit (PKEU) supporting the following:

– RSA and Diffie-Hellman

– Programmable field size up to 2048 bits

– Elliptic curve cryptography

– F2m and F(p) modes

– Programmable field size up to 511 bits

— Data encryption standard execution unit (DEU)

–DES, 3DES

– Two key (K1, K2) or three key (K1, K2, K3)

– ECB and CBC modes for both DES and 3DES

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