LC35256DM datasheet(7/8 Pages) SANYO

Nome de Peças	LC35256DM

Descrição Electrónicos	Dual Control Pins: OE and CE 256K (32768-word X 8-bit) SRAM

PDF	8 Pages

Scroll/Zoom	100%

Fabricante Electrônico	SANYO [Sanyo Semicon Device]

Página de início	https://www.sanyo-av.com/us/

Logo

7 / 8 page

No. 5823-7/8

LC35256D-10, LC35256DM, DT-70/10

Write Cycle 1 (WE write) *6

Write Cycle 2 (CE write) *6

Notes: 1. Applications must set WE high during the read cycle.

2. External circuits in the application must not apply reverse phase signals to the DOUT pins when those pins are in the output state.

3. The time tWP is the period when CE and WE are both low. It is defined as the time from the fall of WE to the rise of CE or the rise of WE, whichever

occurs first.

4. The time tCW is the period when CE and WE are both low. It is defined as the time from the fall of CE to the rise of CE or the rise of WE, whichever

occurs first.

5. The data outputs (DOUT) go to the high-impedance state if any one of the following conditions hold: OE is high, CE is high, or WE is low.

6. OE must be held either high or low during the write cycle.

7. The DOUT pins have the same phase as the write cycle write data.

LC35256DM Folha de dados(PDF) 7 Page - Sanyo Semicon Device

LC35256DM Folha de dados(HTML) 7 Page - Sanyo Semicon Device

Html Pages

1 2 3 4 5 6 7 8

Folha de dados Download

Ligação URL