ADSP-BF504 datasheet(6/80 Pages) AD

6 / 80 page

Rev. PrC

Page 6 of 80

January 2010

ADSP-BF504/F,ADSP-BF506F

Preliminary Technical Data

Booting

The processor contains a small on-chip boot kernel, which con-

figures the appropriate peripheral for booting. If the processor is

configured to boot from boot ROM memory space, the proces-

sor starts executing from the on-chip boot ROM. For more

information, see Booting Modes on Page 16.

Event Handling

The event controller on the processor handles all asynchronous

and synchronous events to the processor. The processor pro-

vides event handling that supports both nesting and

prioritization. Nesting allows multiple event service routines to

be active simultaneously. Prioritization ensures that servicing of

a higher-priority event takes precedence over servicing of a

lower-priority event. The controller provides support for five

different types of events:

• Emulation – An emulation event causes the processor to

enter emulation mode, allowing command and control of

the processor via the JTAG interface.

• Reset – This event resets the processor.

• Nonmaskable Interrupt (NMI) – The NMI event can be

generated either by the software watchdog timer, by the

NMI input signal to the processor, or by software. The

NMI event is frequently used as a power-down indicator to

initiate an orderly shutdown of the system.

• Exceptions – Events that occur synchronously to program

flow (in other words, the exception is taken before the

instruction is allowed to complete). Conditions such as

data alignment violations and undefined instructions cause

exceptions.

• Interrupts – Events that occur asynchronously to program

flow. They are caused by input signals, timers, and other

peripherals, as well as by an explicit software instruction.

Each event type has an associated register to hold the return

address and an associated return-from-event instruction. When

an event is triggered, an interrupt service routine (ISR) must

save the state of the processor to the supervisor stack.

The processor event controller consists of two stages: the core

event controller (CEC) and the system interrupt controller

(SIC). The core event controller works with the system interrupt

controller to prioritize and control all system events. Conceptu-

ally, interrupts from the peripherals enter into the SIC and are

then routed directly into the general-purpose interrupts of the

CEC.

Core Event Controller (CEC)

The CEC supports nine general-purpose interrupts (IVG15–7),

in addition to the dedicated interrupt and exception events. Of

these general-purpose interrupts, the two lowest-priority

interrupts (IVG15–14) are recommended to be reserved for

software interrupt handlers, leaving seven prioritized interrupt

inputs to support the peripherals of the processor. Table 2

describes the inputs to the CEC, identifies their names in the

event vector table (EVT), and lists their priorities.

System Interrupt Controller (SIC)

The system interrupt controller provides the mapping and rout-

ing of events from the many peripheral interrupt sources to the

prioritized general-purpose interrupt inputs of the CEC.

Although the processor provides a default mapping, the user

can alter the mappings and priorities of interrupt events by writ-

ing the appropriate values into the interrupt assignment

registers (SIC_IARx). Table 3 describes the inputs into the SIC

and the default mappings into the CEC.

Table 2. Core Event Controller (CEC)

Priority

(0 is Highest)

Event Class

EVT Entry

0Emulation/Test Control

EMU

Reset

RST

Nonmaskable Interrupt

NMI

3Exception

EVX

Reserved

—

Hardware Error

IVHW

Core Timer

IVTMR

General-Purpose Interrupt 7

IVG7

General-Purpose Interrupt 8

IVG8

General-Purpose Interrupt 9

IVG9

General-Purpose Interrupt 10

IVG10

General-Purpose Interrupt 11

IVG11

General-Purpose Interrupt 12

IVG12

General-Purpose Interrupt 13

IVG13

General-Purpose Interrupt 14

IVG14

General-Purpose Interrupt 15

IVG15

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