ADSP-BF504 datasheet(39/80 Pages) AD

39 / 80 page

Preliminary Technical Data

Rev. PrC

Page 39 of 80

January 2010

ADSP-BF504/F,ADSP-BF506F

Figure 18. Serial Ports

Table 30. Serial Ports—Enable and Three-State

Parameter

DDEXT=1.8 V

DDEXT=2.5/3.3 V

Min

Max

Min

Max

Unit

Switching Characteristics

tDTENE

Data Enable Delay from External TSCLKx1

0.0

tDDTTE

Data Disable Delay from External TSCLKx1

10.0

tDTENI

Data Enable Delay from Internal TSCLKx1

–2.0

tDDTTI

Data Disable Delay from Internal TSCLKx

3.0

1 Referenced to drive edge.

Figure 19. Serial Ports — Enable and Three-State

tSDRI

RSCLKx

RFSx

DRx

DRIVE EDGE

tHDRI

tSFSI

tHFSI

tDFSI

tHOFSI

tSCLKIW

DATA RECEIVE—INTERNAL CLOCK

tSDRE

DATA RECEIVE—EXTERNAL CLOCK

RSCLKx

RFSx

DRx

tHDRE

tSFSE

tHFSE

tDFSE

tSCLKEW

tHOFSE

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RSCLKx OR TSCLKx CAN BE USED AS THE ACTIVE SAMPLING EDGE.

tDDTI

tHDTI

TSCLKx

TFSx

DTx

tSFSI

tHFSI

tSCLKIW

tDFSI

tHOFSI

DATA TRANSMIT—INTERNAL CLOCK

tDDTE

tHDTE

TSCLKx

TFSx

DTx

tSFSE

tDFSE

t SCLKEW

tHOFSE

DATA TRANSMIT—EXTERNAL CLOCK

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RSCLKx OR TSCLKx CAN BE USED AS THE ACTIVE SAMPLING EDGE.

SAMPLE EDGE

DRIVE EDGE

SAMPLE EDGE

DRIVE EDGE

SAMPLE EDGE

DRIVE EDGE

SAMPLE EDGE

tSCLKE

tHFSE

TSCLKx

DTx

DRIVE

tDDTTE/I

tDTENE/I

DRIVE

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