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Os motores de busca de Datasheet de Componentes eletrônicos |
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Os motores de busca de Datasheet de Componentes eletrônicos |
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XIO2001IPNP Folha de dados(PDF) 18 Page - Texas Instruments |
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XIO2001IPNP Folha de dados(HTML) 18 Page - Texas Instruments |
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18 / 131 page  XIO2001 SCPS212D – MAY 2009 – REVISED JANUARY 2010 www.ti.com Table 2-5. PCI System Terminals (continued) ZGU ZAJ PNP I/O CELL CLAMP EXTERNAL SIGNAL DESCRIPTION BALL # BALL # PIN # TYPE TYPE RAIL PARTS C/BE[3] N01 M03 36 I/O PCI PCIR PCI command byte enables C/BE[2] J03 K01 25 Bus – C/BE[1] F02 F03 14 C/BE[0] B01 C02 3 CLK F03 F01 13 I PCI PCIR PCI clock input. This is the clock input – Bus to the PCI bus core. CLKOUT0 B05 B05 120 O PCI PCIR PCI clock outputs. These clock outputs CLKOUT1 B06 B06 117 Bus are used to clock the PCI bus. If the CLKOUT2 A07 B07 114 bridge PCI bus clock outputs are used, CLKOUT3 B07 A07 112 – then CLKOUT6 must be connected to CLKOUT4 A09 A08 107 the CLK input. CLKOUT5 A10 A10 104 CLKOUT6 B11 C10 99 DEVSEL H02 H02 20 I/O PCI PCIR Pullup PCI device select Bus resistor per PCI spec FRAME J02 J01 24 I/O PCI PCIR Pullup PCI frame Bus resistor per PCI spec GNT5 B10 B11 101 O PCI PCIR PCI grant outputs. These signals are GNT4 A11 B10 103 Bus used for arbitration when the PCI bus GNT3 B09 B09 106 is the secondary bus and an external – GNT2 B08 B08 109 arbiter is not used. GNT0 is used as GNT1 C06 A06 115 the REQ for the bridge when an GNT0 A05 A05 118 external arbiter is used. INTA M06 N06 47 I PCI PCIR PCI interrupts A–D. These signals are Pullup INTB N06 L06 48 Bus interrupt inputs to the bridge on the resistor per INTC M07 M07 49 secondary PCI bus. PCI spec INTD L07 N07 50 IRDY J01 H03 23 I/O PCI PCIR Pullup PCI initiator ready Bus resistor per PCI spec LOCK M08 N08 54 I/O PCI PCIR This terminal functions as PCI LOCK Bus when bit 12 (LOCK_EN) is set in the general control register (see Pullup Section 4.65). resistor per PCI spec Note: In lock mode, an external pullup resistor is required to prevent the LOCK signal from floating. M66EN L06 M06 45 I PCI PCIR 66-MHz mode enable Bus 0 = Secondary PCI bus and clock outputs operate at 33 MHz. If Pullup PCLK66_SEL is low then the resistor per frequency will be 25 MHz. PCI spec 1 = Secondary PCI bus and clock outputs operate at 66 MHz. If PCLK66_SEL is low then the frequency will be 50 MHz. PAR F01 G01 15 I/O PCI PCIR PCI bus parity – Bus PERR G02 G03 17 I/O PCI PCIR Pullup PCI parity error Bus resistor per PCI spec PME L12 M12 67 I LV VDD_33_ Pullup resistor per PCI spec PCI power CMOS COMBIO management event. This terminal may Pullup be used to detect PME events from a resistor per PCI device on the secondary bus. PCI spec Note: The PME input buffer has hysteresis. 18 Overview Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): XIO2001 |
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