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XIO2001IPNP Folha de dados(PDF) 62 Page - Texas Instruments

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Nome de Peças XIO2001IPNP
Descrição Electrónicos  PCI Express??to PCI Bus Translation Bridge
PDF  131 Pages
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Fabricante Electrônico  TI [Texas Instruments]
Página de início  http://www.ti.com
Logo TI - Texas Instruments

XIO2001IPNP Folha de dados(HTML) 62 Page - Texas Instruments

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XIO2001
SCPS212D – MAY 2009 – REVISED JANUARY 2010
www.ti.com
BIT NUMBER
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RESET STATE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESET STATE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4-22. MSI Message Lower Address Register Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
31:2
ADDRESS
RW
System specified message address
1:0
RSVD
R
Reserved. Returns 00b when read.
4.44 MSI Message Upper Address Register
This register contains the upper 32 bits of the address that a MSI message writes to when a serial IRQ is
detected. If this register contains 0000 0000h, then 32-bit addressing is used; otherwise, 64-bit addressing
is used.
PCI register offset:
58h
Register type:
Read/Write
Default value:
0000 0000h
BIT NUMBER
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RESET STATE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESET STATE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
4.45 MSI Message Data Register
This register contains the data that software programmed the bridge to send when it send a MSI message.
See Table 4-23 for a complete description of the register contents.
PCI register offset:
5Ch
Register type:
Read/Write
Default value:
0000h
BIT NUMBER
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESET STATE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4-23. MSI Message Data Register Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
15:4
MSG
RW
System specific message. This field contains the portion of the message that the bridge
forwards unmodified.
3:0
MSG_NUM
RW
Message number. This portion of the message field may be modified to contain the
message number is multiple messages are enable. The number of bits that are modifiable
depends on the number of messages enabled in the message control register.
1 message = No message data bits can be modified (default)
2 messages = Bit 0 can be modified
4 messages = Bits 1:0 can be modified
8 messages = Bits 2:0 can be modified
16 messages = Bits 3:0 can be modified
62
Classic PCI Configuration Space
Copyright © 2009–2010, Texas Instruments Incorporated
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