ADC1115S125 datasheet(9/35 Pages) NXP

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ADC1115S125_1

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Preliminary data sheet

Rev. 01 — 12 April 2010

9 of 35

NXP Semiconductors

ADC1115S125

11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs

10.2 Clock and digital output timing

[1]

Typical values measured at VDDA(3V) =3 V, VDDO = 1.8 V, VDDA(5V) =5V; Tamb =25 °C and CL = 5 pF; minimum and maximum values

are across the full temperature range Tamb = −40 °C to +85 °C at VDDA(3V) =3V, VDDO = 1.8 V, VDDA(5V) =5V, VINP − VINM = −1 dBFS;

internal reference mode; applied to CMOS and LVDS interface; unless otherwise specified.

[2]

Measured between 20 % to 80 % of VDDO.

[3]

Rise time measured from

−50 mV to +50 mV; fall time measured from +50 mV to −50 mV.

Table 8.

Clock and digital output timing characteristics[1]

Symbol

Parameter

Conditions

ADC1115S125

Unit

Min

Typ

Max

Clock timing input: pins CLKP and CLKM

fclk

clock frequency

100

125

MHz

tlat(data)

data latency time

clock

cycles

clk

clock duty cycle

DCS_EN = 1

DCS_EN = 0

td(s)

sampling delay time

0.8

twake

wake-up time

tbd

CMOS mode timing output: pins D10 to D0 and DAV

tPD

propagation delay

DATA

3.9

DAV

4.2

tsu

set-up time

4.3

hold time

3.5

rise time[2]

DATA

0.5

2.4

DAV

0.5

2.4

fall time[2]

DATA

0.5

2.4

LVDS DDR mode timing output: pins D10P to D0P, D10M to D0M, DAVP and DAVM

tPD

propagation delay

DATA

3.9

DAV

4.2

tsu

set-up time

1.4

hold time

2.0

rise time[3]

DATA

100

200

DAV

100

200

fall time[3]

DATA

100

200

DAV

100

200

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