MAXQ7666 datasheet(5/49 Pages) MAXIM

5 / 49 page

16-Bit, RISC, Microcontroller-Based,

Smart Data-Acquisition System

_______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(AVDD = DVDDIO = +5.0V, DVDD = +3.3V, fSYSCLK = 8MHz, VREFDAC = VREFADC = +5V, TA = TMIN to TMAX, unless otherwise noted.

Typical values are at TA = +25°C.) (Note 1)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

ANALOG SENSE PATH

Resolution

NADC

No missing codes

Bits

Gain = 1, bipolar mode, VIN = ±2500mV,

500ksps

±0.5

±4.0

Gain = 8, unipolar mode, VIN = +400mV,

142ksps

±2.0

Gain = 16, bipolar mode, VIN = ±156mV,

142ksps

±2.0

±4.0

Integral Nonlinearity

INLADC

Gain = 32, bipolar mode, VIN = ±50mV,

142ksps

±2.0

LSB

Gain = 1, bipolar, VIN = ±2500mV, 500ksps

±1.0

Gain = 16, bipolar, VIN = ±156mV, 142ksps

±1.0

Differential Nonlinearity

DNLADC

All other gain settings

±0.6

LSB

Offset Error

Input referred

±3.2

±5

Offset-Error Temperature

Coefficient

±8

µV/°C

Zero-Code Error

Bipolar, differential measurement of error for

ideal ADC output of 0x000

±3.2

Gain Error

Exclude offset and reference error

-1.0

+1.0

Gain-Error Temperature

Coefficient

±8.5

ppm/°C

Signal-to-Noise Plus Distortion

SINAD

PGA gain = 1V/V

-71

Total Harmonic Distortion

THD

PGA gain = 1V/V

-85

Spurious-Free Dynamic Range

SFDR

PGA gain = 1V/V

-91

Input referred, gain = 1

0.2

Noise

Input referred, gain = 32

3.6

LSBRMS

ADC Convert Start Pulse Width

Minimum pulse width on P0.4/ADCCNV or a

timer port when triggering the ADC

ADC

CLK

Conversion Clock Frequency

fADCCLK

fSYSCLK = 8MHz

0.5

8.0

MHz

PGA gain = 1V/V, RSOURCE

≤ 1kΩ

500

Sample Rate

fSAMPLE

Any PGA gain setting > 1V/V, RSOURCE

≤

Ω

142

ksps

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