MAXQ7666 datasheet(7/49 Pages) MAXIM

7 / 49 page

16-Bit, RISC, Microcontroller-Based,

Smart Data-Acquisition System

_______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(AVDD = DVDDIO = +5.0V, DVDD = +3.3V, fSYSCLK = 8MHz, VREFDAC = VREFADC = +5V, TA = TMIN to TMAX, unless otherwise noted.

Typical values are at TA = +25°C.) (Note 1)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

PGA gain = 1V/V

180

PGA gain = 2V/V

140

PGA gain = 4V/V

120

PGA gain = 8V/V

100

PGA gain = 16V/V

Large-Signal Bandwidth (-3dB)

VIN x gain = 3.2VP-P

PGA gain = 32V/V

MHz

PGA gain = 1V/V

13.6

PGA gain = 2V/V

PGA gain = 4V/V

PGA gain = 8V/V

PGA gain = 16V/V

Input Capacitance

Differential to AGND,

any input of

AIN0–AIN15

PGA gain = 32V/V

Crosstalk Between Channels

AIN15–AIN0, VIN = 1VP-P, 10kHz, RSOURCE

= 5k

Ω

-80

Input Common-Mode Rejection

Ratio

CMRR

AIN15–AIN0 (bipolar, differential),

VCM = 100mV to 4.5V

Power-Supply Rejection Ratio

PSRR

AVDD = +4.75V to +5.25V

DAC SECTION (DACOUT, RL = 5k

Ω and CL = 100pF)

Resolution

NDAC

Guaranteed monotonic

Bits

Differential Nonlinearity

DNLDAC

Codes 147h to E68h

±0.4

±1

LSB

Integral Nonlinearity

INLDAC

Codes 147h to E68h

±0.5

±4

LSB

Offset Error

Reference to code 040h

±2.5

±30

Offset-Error Temperature

Coefficient

±5

µV/°C

Gain Error

Excludes reference error, tested at E68h

±3

±20

LSB

Gain-Error Temperature

Coefficient

Excludes offset and reference drift;

calculated from FSR

±2

ppm of

FSR/°C

DAC Output Range

No load

VREFDAC

DAC enabled

0.5

Ω

DC Output Impedance

ZOUT

Termination resistance

to AGND

Power-down mode

105

Ω

Output Slew Rate

400h to C00h code swing, rising or falling

0.6

V/µs

Output Settling Time

147h to E68h code swing, settling to ±0.5

LSB (Note 6)

815

µs

Short to AGND

Output Short-Circuit Current

Short to AVDD

-46

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