AT697F datasheet(42/155 Pages) ATMEL

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7703C–AERO–6/09

AT697F ADVANCE INFORMATION

Figure 28. Memory Organization when EDAC enabled

data1 byte0

data1 byte1

data1 byte2

data1 byte3

data2 byte0

data2 byte1

data2 byte2

data2 byte3

checksum2

checksum1

rre

spo

ing

eck

sum

0x00000007

0x00000006

0x00000005

0x00000004

0x00000003

0x00000002

0x00000001

0x00000000

0x0FFFFFFF

0x0FFFFFFE

memory top address

Note In addition, only byte-writes shall be performed to ROM area when the EDAC is enabled. In

this case, only the corresponding byte are written.

EDAC testing

The operation of the EDAC can be tested trough the MCFG3 memory configuration register.

Figure 29.

Memory Configuration Reg.

MCFG3

CB[7:0]

EDAC

TCB

EDAC testing overview

Write test

If the write bypass MCFG3

WB is set logical one, the value of the test checksum from the

MCFG3 TCB field replaces the normal checkbits during memory write transactions.

Read test

During memory read transactions, if the read bypass MCFG3 RB is set logical one, the mem-

ory checkbits of the loaded data is stored to the test checkbit MCFG3 TCB.

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