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SPT7936

CLOCK

The SPT7936 accepts a +3.3 V CMOS logic level at the CLK

input. The duty cycle of the clock should be kept as close to

50% as possible. Because consecutive stages in the ADC are

clocked in opposite phase to each other, a non-50% duty

cycle reduces the settling time available for every other stage,

thus potentially causing a degradation of dynamic performance.

For optimal performance at high input frequencies, the clock

should have low jitter and fast edges. The rise/fall times

should be kept shorter than 3 ns. Overshoot and undershoot

should be avoided. Clock jitter causes the noise floor to rise

proportional to the input frequency. Because jitter can be

caused by crosstalk on the PC board, it is recommended that

the clock trace be kept as short as possible and standard

transmission line practices be followed.

DIGITAL OUTPUTS

The digital output data appears in an offset binary code at

3.3 V CMOS logic levels. A negative full scale input results in

an all zeros output code (000…0). A positive full scale input

results in an all 1’s code (111…1). The output data is available

8 clock cycles after the data is sampled. The input signal is

sampled on the high to low transition of the input clock. Output

data should be latched on the low to high clock transition as

shown in figure 1, the Timing Diagram. The output data is

invalid for the first 20 clock cycles after the device is powered up.

OUT OF RANGE OUTPUT (OR)

The digital output OR goes to a logic high to indicate that the

analog input is out of range.

EVALUATION BOARD

The EB7936 Evaluation Board is available to aid designers in

demonstrating the full performance capability of the SPT7936.

The board includes an on-board clock driver, adjustable

voltage references, adjustable bias current circuits, single-to-

differential input buffers with adjustable levels, a single-to-

differential transformer (1:1), digital output buffers and 3.3/5 V

adjustable logic outputs. An application note (AN7936) is also

available which describes the operation of the evaluation

board and provides an example of the recommended power

and ground layout and signal routing. Contact the factory for

price and availability.

PACKAGE OUTLINE

44L TQFP

INCHES

MILLIMETERS

SYMBOL

MIN

MAX

MIN

MAX

A

0.472 Typ

12.00 Typ

B

0.394 Typ

10.00 Typ

C

0.394 Typ

10.00 Typ

D

0.472 Typ

12.00 Typ

E

0.031 Typ

0.80 Typ

F

0.012

0.018

0.300

0.45

G

0.053

0.057

1.35

1.45

H

0.002

0.006

0.05

0.15

I

0.018

0.030

0.450

0.750

J

0.039 Typ

1.00 Typ

K

0-7

°

0-7

°

Index

A

B

C

D

Pin 1

E

F

G

H

I

J

K