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PCS2P5T907A Folha de dados(PDF) 14 Page - PulseCore Semiconductor |
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PCS2P5T907A Folha de dados(HTML) 14 Page - PulseCore Semiconductor |
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14 / 21 page ![]() September 2006 PCS2P5T907A rev 0.2 2.5V Single Data Rate 1:10 Clock Buffer Terabuffer 14 of 21 Notice: The information in this document is subject to change without notice. AC Electrical Characteristics Over Operating Range 7 Symbol Parameter Min Typ Max Unit Skew Parameters Single-Ended and Differential Modes 25 tSK(O) Same Device Output Pin-to- Pin Skew 1 Single-Ended in Differential Mode (DSE) 25 pS Single-Ended and Differential Modes 300 tSK(P) 2 Pulse Skew 3 Single-Ended in Differential Mode (DSE) 300 pS Single-Ended and Differential Modes 350 tSK(P) 4 Pulse Skew 3 Single-Ended in Differential Mode (DSE) 350 pS dT 5 Duty Cycle 40 60 % Single-Ended and Differential Modes 300 tSK(PP) Part-to-Part Skew 6 Single-Ended in Differential Mode (DSE) 300 pS Propagation Delay tPLH tPHL Propagation Delay A to Qn 2.5 nS 2.5V/1.8V LVTTL Outputs 350 1050 tR Output Rise Time (20% to 80%) HSTL / eHSTL Outputs 350 1350 pS 2.5V/1.8V LVTTL Outputs 350 1050 tF Output Fall Time (20% to 80%) HSTL / eHSTL Outputs 350 1350 pS Frequency Range (HSTL/eHSTL outputs) 250 fO Frequency Range (2.5V/1.8V LVTTL outputs) 200 MHz Output Gate Enable/Disable Delay tPGE Output Gate Enable to Qn 3.5 nS tPGD Output Gate Enable to Qn Driven to GL Designated Level 3 nS NOTES: 1. Skew measured between all outputs under identical input and output interfaces, transitions, and load conditions on any one device. 2. For 1.8V LVTTL and eHSTL outputs only. 3. Skew measured is difference between propagation times tPLH and tPHL of any output under identical input and output interfaces, transitions, and load conditions on any one device. 4. For 2.5V LVTTL outputs only. 5. For HSTL outputs only. 6. Skew measured is the magnitude of the difference in propagation times between any outputs of two devices, given identical transitions and load conditions at identical VDD/VDDQ levels and temperature. 7. Guaranteed by design. |
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