S12CPUV2 datasheet(21/138 Pages) MOTOROLA

21 / 138 page

MC9S12DT128 Device User Guide — V02.09

–

The Byteflight pin functionality (BF_PSLM, BF_PERR, BF_PROK, BF_PSYN, TX_BF,

RX_BF) is not available on port PM7, PM6, PM5, PM4, PM3 and PM2, if using a derivative

without Byteflight (see Table 0-1).

–

Do not write MODRR1 and MODRR0 Bit of Module Routing Register (PIM_9DTB128 Block

User Guide), if using a derivative without CAN0 (see Table 0-1).

–

Do not write MODRR3 and MODRR2 Bit of Module Routing Register (PIM_9DTB128 Block

User Guide), if using a derivative without CAN4 (see Table 0-1).

•

Pins not available in 80 pin QFP package for MC9S12DG128E, MC9S12DG128,

MC9S12DJ128E, and MC9S12DJ128

–

Port H

In order to avoid floating nodes the ports should be either configured as outputs by setting the

data direction register (DDRH at Base+$0262) to $FF, or enabling the pull resistors by writing

a $FF to the pull enable register (PERH at Base+$0264).

–

Port J[1:0]

Port J pull-up resistors are enabled out of reset on all four pins (7:6 and 1:0). Therefore care must

be taken not to disable the pull enables on PJ[1:0] by clearing the bits PERJ1 and PERJ0 at

Base+$026C.

–

Port K

Port K pull-up resistors are enabled out of reset, i.e. Bit 7 = PUKE = 1 in the register PUCR at

Base+$000C. Therefore care must be taken not to clear this bit.

–

Port M[7:6]

PM7:6 must be configured as outputs or their pull resistors must be enabled to avoid floating

inputs.

–

Port P6

PP6 must be configured as output or its pull resistor must be enabled to avoid a floating input.

–

Port S[7:4]

PS7:4 must be configured as outputs or their pull resistors must be enabled to avoid floating

inputs.

–

PAD[15:8] (ATD1 channels)

Out of reset the ATD1 is disabled preventing current flows in the pins. Do not modify the ATD1

registers!

•

Pins not available in 80 pin QFP package for MC9S12DB128

–

Port H

In order to avoid floating nodes the ports should be either configured as outputs by setting the

data direction register (DDRH at Base+$0262) to $FF, or enabling the pull resistors by writing

a $FF to the pull enable register (PERH at Base+$0264).

–

Port J[7:6, 1:0]

Port J pull-up resistors are enabled out of reset on all four pins (7:6 and 1:0). Therefore care must

be taken not to disable the pull enables on PJ[7:6, 1:0] by clearing the bits PERJ7, PERJ6,

PERJ1 and PERJ0 at Base+$026C.

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